AME, Inc.
µProcessor Supervisory
AME8500 / 8501
n Timing Diagram
VRelease
VTH
VDD
TD2
50%
TD1
50%
50%
RESET
TD2
50%
TD1
RESETB
n Applications Information
Supply Transients
These devices have a certain immunity to fast negative
going transients. In the following pages the graph titled
“Glitch Rejection” indicates the maximum allowable glitch
amplitude and duration to avoid triggering an unintended
reset. As shown in the graph shorter transients can have
larger amplitudes without triggering resets.
Glitch Rejection
Reset Time vs. Temperature
220
215
210
205
200
195
190
140
120
100
80
60
40
20
0
AME8500AEETAF26
-45
-5
25
55
85
115
0.01
0.1
1
Temperature (oC)
Glitch Amplitude (V)
10