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AME7106RCPL 参数 Datasheet PDF下载

AME7106RCPL图片预览
型号: AME7106RCPL
PDF下载: 下载PDF文件 查看货源
内容描述: 3-1 / 2位A / D转换器的高精度,低功耗 [3-1/2 Digit A/D Converter High Accuracy, Low Power]
分类和应用: 转换器
文件页数/大小: 20 页 / 1428 K
品牌: AME [ ANALOG MICROELECTRONICS ]
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AME, Inc.
AME7106/AME7106A/AME7106R
AME7107/AME7107A/AME7107R
3-1/2 Digit A/D Converter
High Accuracy, Low Power
Auto-Zero Phase:
1000 to 3000 Counts
Signal Integration Phase:
1000 Counts (Fixed)
Reference Integration Phase : 0 to 2000 Counts
n
Digital Section
Digital Ground
AME7106 generates an internal digital ground, typically
5V below the V+. The digital ground of AME7107 is
supplied externally.
Clock Circuit
The clock can be generated in either of the following
three methods.
1. An external oscillator connected to“OSC1”
2. A crystal between pins” OSC1” and “OOSC2”
3. A R-C oscillator using “OOSC1”, “OOSC2” and
“OSC3”
Notes: There is no on-chip feedback resister across osc1
and osc2.
For signals less than full-The
A/D conversion has the
following three phases:scale,
the unused reference
integration time is assigned to the autozero phase.
Segment Drivers (AME7106)
The backplane frequency is 1/800 of the oscillator clock
frequency. For example if the oscillator frequency is
48 KHz (3 conversions per second) the backplane fre-
quency will be 60 Hz. The segment and backplane are
at the same frequency with a nominal 5 volt amplitude.
The segment is visible (ON) when the segment and the
backplane are out of phase, otherwise it is invisible
(OFF). The polarity segment is “ON” for negative ana-
log inputs. When the TEST pin on the AME7106 is
pulled to V+, all segments are turned “ON”. The dis-
play reads -1888. During this mode the LCD segments
have a constant DC voltage impressed. DO NOT LEAVE
THE DISPLAY IN THIS MODE FOR MORE THAN
SEVERAL MINUTES! LCD displays may be destroyed
if operated with DC levels for extended periods.
Systems Timing
The oscillator frequency is divided by 4 prior to clock-
ing the internal decade counters. Each conversion takes
4000 counts or 16000 oscillator clock pulses. The tim-
ing of each phase are as follows:
10