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PALCE16V8H-5JC 参数 Datasheet PDF下载

PALCE16V8H-5JC图片预览
型号: PALCE16V8H-5JC
PDF下载: 下载PDF文件 查看货源
内容描述: EE CMOS 20引脚通用可编程阵列逻辑 [EE CMOS 20-Pin Universal Programmable Array Logic]
分类和应用:
文件页数/大小: 26 页 / 221 K
品牌: AMD [ AMD ]
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AMD  
specification. The design specification is processed by  
development software to verify the design and create a  
programming file (JEDEC). This file, once downloaded  
to a programmer, configures the device according to the  
user’s desired function.  
FUNCTIONAL DESCRIPTION  
The PALCE16V8 is a universal PAL device. It has eight  
independently configurable macrocells (MC0MC7).  
Each macrocell can be configured as registered output,  
combinatorial output, combinatorial I/O or dedicated in-  
put. The programming matrix implements a program-  
mable AND logic array, which drives a fixed OR logic  
array. Buffers for device inputs have complementary  
outputs to provide user-programmable input signal po-  
larity. Pins 1 and 11 serve either as array inputs or as  
clock (CLK) and output enable (OE), respectively, for all  
flip-flops.  
The user is given two design options with the  
PALCE16V8. First, it can be programmed as a standard  
PAL device from the PAL16R8 and PAL10H8 series.  
The PAL programmer manufacturer will supply device  
codes for the standard PAL device architectures to be  
used with the PALCE16V8. The programmer will pro-  
gram the PALCE16V8 in the corresponding architec-  
ture. This allows the user to use existing standard PAL  
device JEDEC files without making any changes to  
them. Alternatively, the device can be programmed as  
aPALCE16V8. HeretheusermustusethePALCE16V8  
device code. This option allows full utilization of the  
macrocell.  
Unused input pins should be tied directly to VCC or GND.  
Product terms with all bits unprogrammed (discon-  
nected) assume the logical HIGH state and product  
terms with both true and complement of any input signal  
connected assume a logical LOW state.  
The programmable functions on the PALCE16V8 are  
automatically configured from the user’s design  
To  
Adjacent  
Macrocell  
1 1  
OE  
1 0  
0 0  
0 1  
1 1  
VCC  
0 X  
1 0  
SL0  
X
SG1  
1 1  
0 X  
I/OX  
D
Q
1 0  
SL1X  
CLK  
Q
1 0  
1 1  
0 X  
From  
Adjacent  
Pin  
*
SG1  
SL0X  
16493D-4  
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.  
PALCE16V8 Macrocell  
PALCE16V8 Family  
2-39  
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