F I N A L
For example, the system could operate at low speeds
during inactivity or polling operations. However, upon
interrupt, the system clock can be increased up to its
maximum speed. After a user-defined time-out period,
the system can be returned to a low (or 0 MHz) operat-
ing speed without losing its state. This design maximiz-
es battery life while achieving optimal performance.
to the SMM code is executed. This Real mode code
can perform its system management function and then
resume execution of the normal system software by ex-
ecuting an RES3 instruction which will reload the saved
processor state and continue execution in the main
system memory space. See Figure 1 for a general flow-
chart of an SMM operation.
CPU Interface—Pin Functions
Benefits of Lower Operating Voltage
(Am386SXLV Only)
The CPU interface for SMM consists of three pins ded-
icated to the SMI function. One pin, SMI, is the interrupt
input. The other two pins, SMIADS and SMIRDY, pro-
vide the control signals necessary for the separate
SMM mode memory space.
The Am386SXLV microprocessor has an operating
voltage range of 3.0 V to 5.5 V. Low voltage allows for
lower operating power consumption, longer battery life,
and/or smaller batteries for portable applications.
Because power is proportional to the square of the volt-
age, reduction of the supply voltage from 5.0 V to 3.3 V
reduces power consumption by 56%. This directly
translates to a doubling of battery life for portable appli-
cations. Lower power consumption can also be used to
reduce the size and weight of the battery. Thus, 3.3-V
designs facilitate a reduction in the form factor.
SMI sampled
active (Low)
Current instruction
finishes execution,
normal ADS goes inactive
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and
provides a less hostile environment for board design.
Lower operating voltage also reduces electromagnetic
radiation noise and makes FCC approval easier to ob-
tain.
CPU saves state to sepa-
rate SMM memory space,
starting at address 60000h
SMM—System Management Mode
(Am386SXLV Only)
CPU enters Real Mode,
starts code fetches at
location FFFFF0h in
SMM memory space
The Am386SXLV microprocessor has a System Man-
agement Mode (SMM) for system and power manage-
ment. This mode consists of two features: System
Management Interrupt (SMI) and I/O instruction break.
SMI—System Management Interrupt
Real Mode SMM interrupt
handler code execution (af-
ter FAR JUMP)
SMI is implemented by using special bus interface
pins. This interrupt method can be used to perform sys-
tem management functions such as power manage-
ment independent of processor operating mode (Real,
Protected, or Virtual 8086 modes).
Restore saved state from
60000h with RES3 (0F 07)
opcode sequence
SMI can also be invoked in software. This allows sys-
tem software to communicate with SMI power manage-
ment code. In addition, the UMOV instruction allows
data transfers between SMI and normal system mem-
ory spaces.
Normal code
execution
resumes
Activating the SMI pin invokes a sequence that saves
the operating state of the processor into a separate
SMM memory space, independent of the main system
memory. After the state is saved, the processor is
forced into Real mode and begins execution at address
FFFFF0h in the SMM memory space where a far jump
16305C–002
Figure 1. SMM Flow
4
Am386SX/SXL/SXLV Microprocessors Data Sheet
AMD [ AMD ]
