P R E L I M I N A R Y
AC CHARACTERISTICS
tWC
Address
CE1#s
tCW
(See Note 2)
tWR (See Note 3)
tAW
tCW (See Note 2)
CE2s
tBW
UB#s, LB#s
tAS
tWP
(See Note 4)
(See Note 5)
WE#
tDW
tDH
Data In
Data Out
Data Valid
High-Z
High-Z
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write
to the end of write.
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
60
Am41DL32x8G
September 5, 2002
AMD [ AMD ]
