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M41000002T 参数 Datasheet PDF下载

M41000002T图片预览
型号: M41000002T
PDF下载: 下载PDF文件 查看货源
内容描述: 32兆位( 4米×8位/ 2的M× 16位) CMOS 3.0伏只,同步读/写闪存和8兆位( 1一M× 8位/ 512的K× 16位)静态RAM [32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM]
分类和应用: 闪存
文件页数/大小: 66 页 / 1128 K
品牌: AMD [ AMD ]
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P R E L I M I N A R Y  
AC CHARACTERISTICS  
tWC  
Address  
tAS (See Note 2 )  
tCW  
tWR (See Note 4)  
(See Note 3)  
CE1#s  
tAW  
CE2s  
tBW  
UB#s, LB#s  
tWP  
(See Note 5)  
WE#  
tDW  
tDH  
Data Valid  
Data In  
Data Out  
High-Z  
High-Z  
Notes:  
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.  
2. tCW is measured from CE1#s going low to the end of write.  
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.  
4. tAS is measured from the address valid to the beginning of write.  
5. A write occurs during the overlap (tWP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when  
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A  
write ends at the earliest transition when CE1#s goes high and WE# goes high. The tWP is measured from the beginning of write  
to the end of write.  
Figure 31. SRAM Write CycleCE1#s Control  
September 5, 2002  
Am41DL32x8G  
59  
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