Table 51. LCD Graphics Controller Cycles—ÉlanSC400 Microcontroller Only
33-MHz
External Bus
Symbol
Parameter Description
Notes
Unit
Min
4T
Max
1
t1a
t1b
t2
SCK period, monochrome panel
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
ns
ns
µs
SCK period, color STN panel
2T
1
1
SCK High time
T
t3
SCK Low time
T
1
t4
Setup, data to SCK falling edge
T-15
T-15
8T
1
t5
Hold, LCD_data from SCK falling edge
Width, LC
1
t6
1,2
1,2
t7
Setup, FRM to LC falling
t8
Hold, FRM from LC falling
t9
Delay, LC falling to M phase change
Delay, power-on sequencing, LVDD to signals
Delay, power-on sequencing, signals to LVEE
Delay, power-off sequencing, LVEE to signals, normal power-down
Delay, power-off sequencing, signals to LVDD, normal power-down
Delay, LVEE to LCD_SIGNALS off, emergency power-down
Delay, LCD_SIGNALS off to LVDD off, emergency power-down
Delay, emergency power-off sequencing from BL2 edge
0
7.8
7.8
62.5
62.5
0
15
3
4
5
6
t11a
t11b
t12a
t12b
t13
t14
t15
62.5
62.5
500
500
0
0
10
Notes:
1. T = period of internal video dot clock—programmable via the Pixel Clock Control Register.
2. Programmable to within resolution of 8T intervals (single-screen mode) or 16T intervals (dual-screen mode).
3. Programmable through PMU Control Register 1, bits 2–0.
4. Programmable through PMU Control Register 1, bits 5–3.
5. Programmable through PMU Control Register 2, bits 2–0.
6. Programmable through PMU Control Register 2, bits 5–3.
t1a,b
t2
t4
t3
t5
SCK
LCDD7–
LCDD0
t7
t9
t6
t8
LC
FRM
M
Figure 63. Graphics Panel Interface Timing (ÉlanSC400 Microcontroller Only)
128
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ AMD ]
