P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Clock and Reset Timing
t
CLK Clock Period
(Note 1)
49.995
50.005
ns
ns
ns
ns
ns
µs
µs
CLK
t
CLK Clock High
20
20
-
30
30
10
10
-
CLKH
t
CLK Clock Low
CLKL
t
CLK Rise Time
(Note 1)
(Note 1)
CLKR
t
CLK Fall Time
-
CLKF
t
Reset Pulse Width (RST pin LOW)
Reset Pulse Width at Power Up
4
RST
t
150
-
PRST
Transmit Timing
t
PDO Pulse Width Accept/ Reject Thresh-
old
Input > V
(Max)
(Max)
15
35
ns
ns
PWODO
ASQ
(Note 3)
t
PDO Pulse Width Maintain/Turn-Off
Threshold
Input > V
110
200
PWKDO
ASQ
(Note 4)
t
Transmit Start-Up Delay
-
-
300
200
ns
ns
TON
t
Transmit Static Propagation Delay (PDO
to TXD)
TSD
t
Transmit End of Transmission (for TXD)
Idle Signal Period
250
8
450
24
ns
ms
ns
TETD
t
(Note 7)
(Note 1)
(Note 7)
(Note 7)
(Note 1)
PERLP
t
Link Pulse Width
75
120
150
750
-
PWLP
t
Transmit Jabber Activation Time
Transmit Jabber Reset Time
Transmit Jabber Recovery Time (Mini-
mum time gap between packets to prevent
Jabber activation)
20
ms
ms
µs
JA
JR
t
250
1.0
t
JREC
t
PDO to PDI Start-up Delay
PDO to PDI Static Propagation Delay
300
100
ns
ns
DODION
t
-
5
DODISD
Receive Timing
t
RXD Pulse Width Accept/Reject
Threshold
(Note 5)
(Note 6)
35
ns
ns
PWORD
t
RXD Pulse Width Maintain/Turn-Off
Threshold
136
200
400
PWKRD
t
Receiver Start-up Delay (RXD to PDI)
First Validly Timed Bits
Receiver Static Propagation Delay (RXD
to PDI)
200
ns
ns
ns
RON
t
t
-
-
t
+100
RVD
RON
70
RSD
t
PDI End of Transmission
PDI, PCI Rise Time
200
-
ns
ns
ns
ns
RETD
t
(Note 1)
(Note 1)
(Note 1)
-
-
-
10
10
5
RR
t
PDI, PCI Fall Time
RF
t
PDI, PCI Rise and Fall Time Mismatch (t
RR
RM
- t
)
RF
Collision Timing
t
Collision Turn On Delay
Collision Turn Off Delay
Collision Period
-
500
500
117
60
ns
ns
ns
ns
CON
t
-
COFF
CPER
t
(Note 1)
(Note 1)
87
40
t
Collision Output Pulse Width
CPW
Serial Interface Timing
t
CLK to DIR Setup Time
DIR Hold Time
(Note 7)
(Note 7)
(Note 7)
(Note 7)
10
10
10
10
-
-
-
ns
ns
ns
ns
ns
SDSU
SDHD
t
t
CLK to SDATA Setup Time
CLK to SDATA Hold Time
CLK to Output Delay
-
SSSU
SSHD
SSDO
t
-
t
40
18
Am79C988A
AMD [ AMD ]
