INTA
IRDY
Interrupt Request
Output
Initiator Ready
Input/Output
An attention signal which indicates that one or more of
the following status flags is set: EXDINT, IDON, MERR,
MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT,
TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MRE-
INT, and STINT. Each status flag has either a mask or
an enable bit which allows for suppression of INTA as-
sertion. Table 1 shows the flag descriptions. By default
INTA is an open-drain output. For applications that
need a high-active edge-sensitive interrupt signal, the
INTA pin can be configured for this mode by setting IN-
TLEVEL (BCR2, bit 7) to Table 1.
IRDY indicates the ability of the initiator of the transac-
tion to complete the current data phase. IRDY is used
in conjunction with TRDY. Wait states are inserted until
both IRDY and TRDY are asserted simultaneously. A
data phase is completed on any clock when both IRDY
and TRDY are asserted.
When the Am79C978 controller is a bus master, it as-
serts IRDY during all write data phases to indicate that
valid data is present on AD[31:0]. During all read data
phases, the device asserts IRDY to indicate that it is
ready to accept the data.
When RST is active, INTA is the output for NAND tree
testing.
When the Am79C978 controller is the target of a trans-
action, it checks IRDY during all write data phases to
determine if valid data is present on AD[31:0]. During
all read data phases, the device checks IRDY to deter-
mine if the initiator is ready to accept the data.
Table 1. Interrupt Flags
Name
Description
Mask Bit
Interrupt Bit
Excessive
Deferral
EXDINT
CSR5, bit 6
CSR5, bit 7
When RST is active, IRDY is an input for NAND tree
testing.
Initialization
Done
IDON
CSR3, bit 8
CSR0, bit 8
PAR
MERR
MISS
Memory Error CSR3, bit 11 CSR0, bit 11
Missed Frame CSR3, bit 12 CSR0, bit 12
Missed Frame
Parity
Input/Output
Parity is even parity across AD[31:0] and C/BE[3:0].
When the Am79C978 controller is a bus master, it gen-
erates parity during the address and write data phases.
It checks parity during read data phases. When the
Am79C978 controller operates in slave mode, it checks
parity during every address phase. When it is the target
of a cycle, it checks parity during write data phases and
it generates parity during read data phases.
MFCO
MPINT
Count Over-
flow
CSR4, bit 8
CSR4, bit 9
CSR5, bit 4
CSR4, bit 5
Magic Packet
Interrupt
CSR5, bit 3
Receive
RCVCCO Collision Count CSR4, bit 4
Overflow
When RST is active, PAR is an input for NAND tree
testing.
Receive
Interrupt
RINT
SINT
TINT
CSR3, bit 10 CSR0, bit 10
System Error CSR5, bit 10 CSR5, bit 11
PERR
Transmit
Interrupt
Parity Error
Input/Output
CSR3, bit 9
CSR0, bit 9
During any slave write transaction and any master read
transaction, the Am79C978 controller asserts PERR
when it detects a data parity error and reporting of the
error is enabled by setting PERREN (PCI Command
register, bit 6) to 1. During any master write transaction,
the Am79C978 controller monitors PERR to see if the
target reports a data parity error.
TXSTRT
UINT
Transmit Start CSR4, bit 2
User Interrupt CSR4, bit 7
CSR4, bit 3
CSR4, bit 6
MII
Management
MCCINT
Command
Complete
Interrupt
CSR7, bit 4
CSR7, bit 5
When RST is active, PERR is an input for NAND tree
MIIPHYDetect
MPDTINT Transition
Interrupt
CSR7, bit 0
CSR7, bit 6
CSR7, bit 1
CSR7, bit 7
testing.
REQ
MII Auto-Poll
MAPINT
Interrupt
Bus Request
Input/Output
MII
The Am79C978 controller asserts REQ pin as a signal
that it wishes to become a bus master. REQ is driven
high when the Am79C978 controller does not request
the bus. In Power Management mode, the REQ pin will
not be driven.
Management
Frame Read
Error Interrupt
MREINT
CSR7, bit 8
CSR7, bit 9
Software Timer
Interrupt
STINT
CSR7, bit 10 CSR7, bit 11
Am79C978
27
AMD [ AMD ]
