Note: The labels in the following text are used as ref-
erences in the timeline diagram that follows (Figure
B-1).
ber 2 will be sufficient or not for this frame, but it has no
way to tell except by trying to move the entire message
into that space. Only when the message does not fit will
it signal a buffer error condition--there is no need to
panic at this point that it discovers that it does not yet
own descriptor number 3.
Setup
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three de-
scriptors to read as follows: 11b, 10b, 00b.
S2
The first task of the drivers interrupt service
routing is to collect the header information
from the controller’s first buffer and pass it to
the application.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the controller to generate an INTERRUPT
when STP has been written to a receive descriptor by
the controller.
S3
The application will return an application buffer
pointer to the driver. The driver will add an off-
set to the application data buffer pointer, since
the controller will be placing the first portion of
the message into the first and second buffers.
(the modified application data buffer pointer
will only be directly used by the controller when
it reaches the third buffer.) The driver will place
the modified data buffer pointer into the final
descriptor of the group (#3) and will grant own-
ership of this descriptor to the controller.
Flow
The controller polls the current receive descriptor at
some point in time before a message arrives. The con-
troller determines that this receive buffer is OWNed by
the controller and it stores the descriptor information to
be used when a message does arrive.
N0
Frame preamble appears on the wire, followed
by SFD and destination address.
C5
S4
Interleaved with S2, S3, and S4 driver activity,
the controller will write frame data to buffer
number 2.
N1
The 64th byte of frame data arrives from the
wire. This causes the controller to begin frame
data DMA operations to the first buffer.
The driver will next proceed to copy the con-
tents of the controller’s first buffer to the begin-
ning of the application space. This copy will be
to the exact (unmodified) buffer pointer that
was passed by the application.
C0
C1
When the 64th byte of the message arrives,
the controller performs a lookahead operation
to the next receive descriptor. This descriptor
should be owned by the controller.
The controller intermittently requests the bus
to transfer frame data to the first buffer as it ar-
rives on the wire.
S5
C6
After copying all of the data from the first buffer
into the beginning of the application data
buffer, the driver will begin to poll the owner-
ship bit of the second descriptor. The driver is
waiting for the controller to finish filling the sec-
ond buffer.
S1
C2
The driver remains idle.
When the controller has completely filled the
first buffer, it writes status to the first descriptor.
At this point, knowing that it had not previously
owned the third descriptor and knowing that
the current message has not ended (there is
more data in the FIFO), the controller will make
a last ditch lookahead to the final (third) de-
scriptor. This time the ownership will be TRUE
(i.e., the descriptor belongs tot he controller),
because the driver wrote the application
pointer into this descriptor and then changed
the ownership to give the descriptor to the con-
troller back at S3. Note that if steps S1, S2,
and S3 have not completed at this time, a
BUFF error will result.
C3
When the first descriptor for the frame has
been written, changing ownership from the
controller to the CPU, the controller will gener-
ate an SRP INTERRUPT. (This interrupt ap-
pears as a RINT interrupt in CSR0).
S1
C4
The SRP INTERRUPT causes the CPU to
switch tasks to allow the controller’s driver to
run.
During the CPU interrupt-generated task
switching, the controller is performing a looka-
head operation to the third descriptor. At this
point in time, the third descriptor is owned by
the CPU.
C7
After filling the second buffer and performing
the last chance lookahead to the next descrip-
tor, the controller will write the status and
change the ownership bit of descriptor number
2.
Note: Even though the third buffer is not owned by the
controller, existing AMD Ethernet controllers will con-
tinue to perform data DMA into the buffer space that the
controller already owns (i.e., buffer number 2). The
controller does not know if buffer space in buffer num-
B-2
Am79C978
AMD [ AMD ]
