SWITCHING WAVEFORMS: SYSTEM BUS INTERFACE (CONTINUED)
Tx
Tx
Tx
CLK
t
VAL
MIN
MIN
MAX
Valid n+1
AD[31:00] C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP, DEVSEL,
PERR, SERR
Valid n
t
VAL(REQ)
MAX
Valid n+1
REQ
Valid n
22206B-63
Figure 60. Output Valid Delay Timing
Tx
Tx
Tx
CLK
t
ON
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
Valid n
DEVSEL, PERR
t
OFF
AD[31:00], C/BE[3:0],
PAR, FRAME, IRDY,
TRDY, STOP,
Valid n
DEVSEL, PERR
22206B-64
Figure 61. Output Tri-State Delay Timing
EESK
EECS
22206B-65
0
1
1
A6 A5
A4
A3
A2
A1 A0
EEDI
EEDO
D15 D14 D13
D2 D1 D0
22206B-65
Figure 62. EEPROM Read Functional Timing
230
Am79C978
AMD [ AMD ]
