P R E L I M I N A R Y
Erase and Programming Performance
Typ (Note
1)
Parameter
Max (Note 2)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
1
14
8
10
Excludes 00h programming
prior to erasure
s
Byte Programming Time
Word Programming Time
300
360
25
µs
µs
s
16
8.4
Excludes system level
overhead (Note 5)
Chip Programming
Time
Byte Mode
Word Mode
5.8
17
s
(Note 3)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles.
CC
Additionally, programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
bytes program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 5 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
Latchup Characteristics
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
12.5 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V
=
CC
CC
3.0 V, one pin at a time.
TSOP and SO Pin Capacitance
Parameter
Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
12
Unit
pF
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
V
= 0
= 0
= 0
IN
IN
C
V
8.5
7.5
pF
OUT
OUT
C
V
9
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
Data Retention
Test
Parameter
Conditions
Min
10
Unit
150°C
Years
Years
Minimum Pattern Data Retention Time
125°C
20
43
Am29LV800D
Am29LV800D_00_A4_E January 21, 2005