D A T A S H E E T
TEST CONDITIONS
Table 11. Test Specifications
All speed
5.0 V
Test Condition
options
Unit
2.7 kΩ
Device
Under
Test
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
20
ns
V
0.45–2.4
Input timing measurement
reference levels
0.8
2.0
V
V
Note: Diodes are IN3064 or equivalent
Output timing measurement
reference levels
Figure 8. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
26
Am29F016D
21444E6 November 1, 2006
AMD [ AMD ]
