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AM29F002NBB-90JC 参数 Datasheet PDF下载

AM29F002NBB-90JC图片预览
型号: AM29F002NBB-90JC
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位( 256千×8位) CMOS 5.0伏只引导扇区闪存 [2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存内存集成电路
文件页数/大小: 42 页 / 800 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
WRITE OPERATION STATUS  
The device provides several bits to determine the  
status of a write operation: DQ2, DQ3, DQ5, DQ6, and  
DQ7. Table 6 and the following subsections describe  
the functions of these bits. DQ7 and DQ6 each offer a  
method for determining whether a program or erase  
operation is complete or in progress. These three bits  
are discussed first.  
Table 6 shows the outputs for Data# Polling on DQ7.  
Figure 4 shows the Data# Polling algorithm.  
START  
DQ7: Data# Polling  
The Data# Polling bit, DQ7, indicates to the host  
system whether an Embedded Algorithm is in progress  
or completed, or whether the device is in Erase Sus-  
pend. Data# Polling is valid after the rising edge of the  
final WE# pulse in the program or erase command  
sequence.  
Read DQ7–DQ0  
Addr = VA  
Yes  
DQ7 = Data?  
During the Embedded Program algorithm, the device  
outputs on DQ7 the complement of the datum pro-  
grammed to DQ7. This DQ7 status also applies to  
programming during Erase Suspend. When the  
Embedded Program algorithm is complete, the device  
outputs the datum programmed to DQ7. The system  
must provide the program address to read valid status  
information on DQ7. If a program address falls within a  
protected sector, Data# Polling on DQ7 is active for  
approximately 2 µs, then the device returns to reading  
array data.  
No  
No  
DQ5 = 1?  
Yes  
Read DQ7–DQ0  
Addr = VA  
During the Embedded Erase algorithm, Data# Polling  
produces a “0” on DQ7. When the Embedded Erase  
algorithm is complete, or if the device enters the Erase  
Suspend mode, Data# Polling produces a “1” on DQ7.  
This is analogous to the complement/true datum output  
described for the Embedded Program algorithm: the  
erase function changes all the bits in a sector to “1”;  
prior to this, the device outputs the “complement,or  
“0.The system must provide an address within any of  
the sectors selected for erasure to read valid status  
information on DQ7.  
Yes  
DQ7 = Data?  
No  
PASS  
FAIL  
After an erase command sequence is written, if all  
sectors selected for erasing are protected, Data#  
Polling on DQ7 is active for approximately 100 µs, then  
the device returns to reading array data. If not all  
selected sectors are protected, the Embedded Erase  
algorithm erases the unprotected sectors, and ignores  
the selected sectors that are protected.  
Notes:  
1. VA = Valid address for programming. During a sector  
erase operation, a valid address is an address within any  
sector selected for erasure. During chip erase, a valid  
address is any non-protected sector address.  
2. DQ7 should be rechecked even if DQꢀ = “1” because  
DQ7 may change simultaneously with DQꢀ.  
When the system detects DQ7 has changed from the  
complement to true data, it can read valid data at DQ7–  
DQ0 on the following read cycles. This is because DQ7  
may change asynchronously with DQ0–DQ6 while  
Output Enable (OE#) is asserted low. The Data#  
Polling Timings (During Embedded Algorithms) figure  
in the “AC Characteristics” section illustrates this.  
Figure 4. Data# Polling Algorithm  
November 1, 2006 21527D5  
Am29F002B/Am29F002NB  
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