D A T A
S H E E T
REVISION SUMMARY
Revision A (January 1998)
Initial release.
Revision A+4 (August 1998)
Ordering Information
Corrected description for E and F package type desig-
nators to 48-pin TSOP.
AC Characteristics
Read Operations: Corrected t
RC
, t
ACC
, t
CE
for 90 ns
speed option.
Diagram
Changed timing parameters to match those in Figure 2.
Revision A+1 (January 1998)
Reset Command
Deleted last paragraph in section, which applied to RESET#,
not the reset command.
Revision A+2 (Febrauary 1998)
Hardware Reset (RESET#)
Added note to table, fixed references to note.
Revision A+3 (April 1998)
Global
Removed references to the 80 ns speed option.
Changed the 70R ns (V
CC
± 5%) speed option to the
70 ns (V
CC
± 10%) speed option.
Figure 2, In-System Sector Protect/Unprotect
Algorithms
In the sector protect algorithm, added a “Reset
PLSCNT=1” box in the path from “Protect another sec-
tor?” back to setting up the next sector address.
DQ6: Toggle Bit I
In the first and second paragraphs, clarified that the
toggle bit may be read “at any address within the pro-
gramming or erasing bank,” not “at any address.” In the
fourth paragraph, clarified “device” to “bank.”
DC Characteristics
Added reference to Note 4 on I
CC6
and I
CC7
specifications.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations:
Corrected the
notes reference for t
WHWH1
and t
WHWH2
. These param-
eters are 100% tested. Corrected the note reference for
t
VCS
. This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for t
VIDR
. This parameter is not
100% tested.
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cycles.
Revision B (January 1999)
Connection Diagrams
Changed FBGA drawing to top view.
Ordering Information
Changed FBGA package reference to FBB048. Added
FBGA package markings to valid combinations table.
Revision B+1 (February 1999)
Physical Dimensions
Corrected ball grid layout on FBB048.
Revision B+2 (July 2, 1999)
Test Conditions
Test Specifications table:
Corrected to indicate that the
70 ns speed is tested at 30 pF loading.
Revision C (December 7, 1999)
AC Characteristics—Figure 17. Program
Operations Timing and Figure 18. Chip/Sector
Erase Operations
Deleted t
GHWL
and changed OE# waveform to start at
high.
Physical Dimensions
Replaced figures with more detailed illustrations.
Revision C+1 (November 21, 2000)
Global
Added table of contents.
Ordering Information
Deleted burn-in option.
December 4, 2006 21519C4
Am29DL800B
43
AMD [ ADVANCED MICRO DEVICES ]
