AC Characteristics—Write/Erase/Program Operations
Parameter Symbols
Am28F256 Speed Options
JEDEC
Standard
Parameter Description
Write Cycle Time (Note 4)
Address Set-up Time
Address Hold Time
-70
70
0
-90
90
0
-120
120
0
-150
150
0
-200
200
0
Unit
ns
t
t
Min
Min
Min
Min
Min
AVAV
WC
t
t
ns
AVWL
WLAX
DVWH
WHDX
AS
AH
DS
DH
t
t
45
45
10
45
45
10
50
60
75
ns
t
t
Data Setup Time
50
50
50
ns
t
t
Data Hold Time
10
10
10
ns
Write Recovery Time
before Read
t
t
t
Min
Min
6
0
6
0
6
0
6
0
6
0
µs
µs
WHGL
GHWL
WR
Read Recovery Time
before Write
t
t
Chip Enable Set-up Time
Chip Enable Hold Time
Write Pulse Width
Min
Min
Min
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ELWL
WHEH
WLWH
CS
CH
WP
t
t
t
t
45
45
50
60
60
Write Pulse
Width HIGH
t
t
Min
Min
Min
Min
Min
Min
Min
Min
20
10
20
10
20
10
20
10
20
10
ns
µs
ms
ns
µs
ns
ns
ns
WHWL
WPH
Duration of Programming
Operation (Note 2)
t
t
WHWH1
WHWH2
Duration of
Erase Operation (Note 2)
9.5
100
50
9.5
100
50
9.5
100
50
9.5
100
50
9.5
100
50
V
Setup Time to
PP
t
VPEL
Chip Enable LOW (Note 4)
V
Set-up Time to
CC
t
VCS
Chip Enable LOW (Note 4)
V
Rise Time
PP
t
500
500
100
500
500
100
500
500
100
500
500
100
500
500
100
VPPR
90% V
(Note 4)
PPH
V
Fall Time
PP
t
VPPF
10% V
(Note 4)
PPL
V
< V
LKO
CC
t
LKO
to Reset (Note 4)
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
4. Not 100% tested.
Am28F256
27
AMD [ AMD ]
