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AM27C512-120DI 参数 Datasheet PDF下载

AM27C512-120DI图片预览
型号: AM27C512-120DI
PDF下载: 下载PDF文件 查看货源
内容描述: 512千比特(一个64 K ×8位) CMOS EPROM [512 Kilobit (64 K x 8-Bit) CMOS EPROM]
分类和应用: 可编程只读存储器电动程控只读存储器
文件页数/大小: 12 页 / 162 K
品牌: AMD [ AMD ]
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FUNCTIONAL DESCRIPTION  
Device Erasure  
OE#/VPP = 12.75 V ± 0.25 V, will program that particu-  
lar device. A high-level CE# input inhibits the other de-  
vices from being programmed.  
In order to clear all locations of their programmed con-  
tents, the device must be exposed to an ultraviolet light  
source. A dosage of 15 W seconds/cm2 is required to  
completely erase the device. This dosage can be ob-  
tained by exposure to an ultraviolet lamp—wavelength  
of 2537 Å—with intensity of 12,000 µW/cm2 for 15 to 20  
minutes. The device should be directly under and about  
one inch from the source, and all filters should be re-  
moved from the UV light source prior to erasure.  
Program Verify  
A verification should be performed on the programmed  
bits to determine that they were correctly programmed.  
The verify should be performed with OE#/VPP and CE#  
at VIL, and VPP between 12.5 V and 13.0 V.  
Autoselect Mode  
Note that all UV erasable devices will erase with light  
sources having wavelengths shorter than 4000 Å, such  
as fluorescent light and sunlight. Although the erasure  
process happens over a much longer time period, ex-  
posure to any light source should be prevented for  
maximum system reliability. Simply cover the package  
window with an opaque label or substance.  
The autoselect mode provides manufacturer and de-  
vice identification through identifier codes on DQ0–  
DQ7. This mode is primarily intended for programming  
equipment to automatically match a device to be pro-  
grammed with its corresponding programming algo-  
rithm. This mode is functional in the 25°C ± 5°C  
ambient temperature range that is required when pro-  
gramming the device.  
Device Programming  
To activate this mode, the programming equipment  
must force VH on address line A9. Two identifier bytes  
may then be sequenced from the device outputs by tog-  
gling address line A0 from VIL to VIH (that is, changing  
the address from 00h to 01h). All other address lines  
must be held at VIL during the autoselect mode.  
Upon delivery, or after each erasure, the device has  
all of its bits in the “ONE”, or HIGH state. “ZEROs” are  
loaded into the device through the programming pro-  
cedure.  
The device enters the programming mode when 12.75  
V ± 0.25 V is applied to the OE#/VPP pin, and CE# is at  
VIL.  
Byte 0 (A0 = VIL) represents the manufacturer code,  
and Byte 1 (A0 = VIH), the device identifier code. Both  
codes have odd parity, with DQ7 as the parity bit.  
For programming, the data to be programmed is ap-  
plied 8 bits in parallel to the data pins.  
Read Mode  
The flowchart in the Programming section of the  
EPROM Products Data Book (Section 5, Figure 5-1)  
shows AMD’s Flashrite algorithm. The Flashrite algo-  
rithm reduces programming time by using a 100 µs pro-  
gramming pulse and by giving each address only as  
many pulses to reliably program the data. After each  
pulse is applied to a given address, the data in that ad-  
dress is verified. If the data does not verify, additional  
pulses are given until it verifies or the maximum pulses  
allowed is reached. This process is repeated while se-  
quencing through each address of the device. This part  
of the algorithm is done at VCC = 6.25 V to assure that  
each EPROM bit is programmed to a sufficiently high  
threshold voltage. After the final address is completed,  
To obtain data at the device outputs, Chip Enable (CE#)  
and Output Enable (OE#/VPP) must be driven low. CE#  
controls the power to the device and is typically used to  
select the device. OE#/VPP enables the device to out-  
put data, independent of device selection. Addresses  
must be stable for at least tACC–tOE. Refer to the  
Switching Waveforms section for the timing diagram.  
Standby Mode  
The device enters the CMOS standby mode when CE#  
is at VCC ± 0.3 V. Maximum VCC current is reduced to  
100 µA. The device enters the TTL-standby mode  
when CE# is at VIH. Maximum VCC current is reduced  
to 1.0 mA. When in either standby mode, the device  
places its outputs in a high-impedance state, indepen-  
dent of the OE# input.  
the entire EPROM memory is verified at VCC = VPP  
5.25 V.  
=
Please refer to Section 5 of the EPROM Products Data  
Book for additional programming information and spec-  
ifications.  
Output OR-Tieing  
To accommodate multiple memory connections, a  
two-line control function provides:  
Program Inhibit  
Low memory power dissipation, and  
Programming different data to multiple devices in par-  
allel is easily accomplished. Except for CE#, all like in-  
puts of the devices may be common. A TTL low-level  
program pulse applied to one device’s CE# input with  
Assurance that output bus contention will not occur.  
CE# should be decoded and used as the primary de-  
vice-selecting function, while OE#/VPP be made a com-  
Am27C512  
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