P R E L I M I N A R Y
Unlike the UCS and LCS chip selects, the PCS outputs
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
A2—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 2 to the system. During a bus hold
condition, A2 retains its previously latched value.
RTS1—This pin provides the Ready to Send signal for
asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 1 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTS1 signal is asserted when the
associated serial port transmit register contains data
which has not been transmitted.
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ES and Am188ES microcontrollers provide
32 individually programmable I/O pins. Each PIO can
be programmed with the following attributes: PIO
function (enabled/disabled), direction (input/output),
and weak pullup or pulldown. The pins that are
multiplexed with PIO31–PIO0 are listed in Table 2 and
Table 3.
RTR1—This pin provides the Ready to Receive signal
for asynchronous serial port 1 when the RTS1 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 1 control
register is set). The RTR1 signal is asserted when the
associated serial port receive register does not contain
valid, unread data.
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset
Status in Table 2 and Table 3 lists the defaults for the
PIOs. Most of the PIO pins are configured as PIO
inputs with pullup after power-on reset. The system
initialization code must reconfigure any PIO pins as
required.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory
access is in progress to the sixth region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS5 is held High
during a bus hold condition. It is also held High during
reset.
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched
address bit 1 to the system. During a bus hold
condition, A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
access is in progress to the seventh region of the
peripheral memory block (either I/O or memory
address space). The base address of the peripheral
memory block is programmable. PCS6 is held High
during a bus hold condition or reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
Am186/188ES and Am186/188ESLV Microcontrollers
33
AMD [ AMD ]
