Date
Rev Description
Under “SRDY/PIO6” on page 38, the following sentence was added: "When SRDY is configured as
P106, the internal SRDY signal is driven Low."
May 2000
D
In Table 8, “Maximum and Minimum Clock Frequencies,” on page 44, the values are changed in the
cell of row "Divide by 2" and column "X1/X2 Min" and in the cell of row "Divide by 2" and column
"CLKOUTA Min".
May 2000
D
In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 93, Max
value in the number "36" row was changed to "33."
May 2000
May 2000
D
D
In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 94, the
value in "40 MHz Max" for row number 36 was changed to "33."
May 2000
May 2000
May 2000
May 2000
May 2000
May 2000
May 2000
May 2000
D
D
D
D
D
D
D
D
In “Synchronous Ready Waveforms” on page 97, the diagram was changed.
In “Asynchronous Ready Waveforms” on page 97, the diagram was changed.
In "BHE/ADEN", on page 31, the second paragraph under ADEN was changed.
In "UZI/CLKSEL2/PIO26", on page 38, the paragraph description of UZI was changed.
In “Read Cycle Waveforms” on page 72, the UZI line in the diagram was changed.
In “Write Cycle Waveforms” on page 75, the UZI line in the diagram was changed.
Added the diagram, Table 11, “ARDY and SRDY Synchronization Logic Diagram,” on page 49.
Added an index.
Am186TMER and Am188TMER Microcontrollers Data Sheet
11
AMD [ AMD ]
