P R E L I M I N A R Y
PIN DESCRIPTIONS
During a power-on reset, the address and data bus
Pins That Are Used by Emulators
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system
configuration information into the internal reset
configuration register.
The following pins are used by emulators: A19–A0,
AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the 186),
CLKOUTA, RFSH2/ADEN (on the 188), RD, S2–S0,
S6/LOCK/CLKDIV2, and UZI.
AO15–AO8—When the address bus is enabled on the
Am188ES microcontroller, via the AD bit in the UMCS
and LMCS registers, the address-only bus (AO15–
AO8) contains valid high-order address bits from bus
cycles t1–t4. These outputs are floated during a bus
hold or reset.
Emulators require S6/LOCK/CLKDIV2 and UZI to be
configured in their normal functionality as S6 and UZI,
not as PIOs. If BHE/ADEN (on the 186) or RFSH2/
ADEN (on the 188) is held Low during the rising edge
of RES, S6 and UZI are configured in their normal
functionality.
On the Am188ES microcontroller, AO15–AO8
combine with AD7–AD0 to form a complete multiplexed
address bus while AD7–AD0 is the 8-bit data bus.
Pin Terminology
The following terms are used to describe the pins:
Input—An input-only pin.
AD7–AD0
Output—An output-only pin.
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
Input/Output—A pin that can be either input or output.
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. This bus
supplies the low-order 8 bits of an address to the
system during the first period of a bus cycle (t1), and it
supplies data to the system during the remaining
periods of that cycle (t2, t3, and t4). In 8-bit mode on the
Am188ES microcontroller, AD7–AD0 supplies the
data.
Synchronous—Synchronous inputs must meet setup
and hold times in relation to CLKOUTA. Synchronous
outputs are synchronous to CLKOUTA.
Asynchronous—Inputs or outputs that are
asynchronous to CLKOUTA.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is deasserted, these pins are three-stated during
t2, t3, and t4.
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O
addresses to the system one half of a CLKOUTA
period earlier than the multiplexed address and data
bus (AD15–AD0 on the 186 or AO15–AO8 and AD7–
AD0 on the 188). During a bus hold or reset condition,
the address bus is in a high-impedance state.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the 186, AO15–AO8 and AD7–
AD0 for the 188) can also be used to load system
configuration information into the internal reset
configuration register.
AD15–AD8 (Am186ES Microcontroller)
AO15–AO8 (Am188ES Microcontroller)
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
Address-Only Bus (output, three-state,
synchronous, level-sensitive)
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address ap-
pears on the address and data bus (AD15–AD0 for the
186 or AO15–AO8 and AD7–AD0 for the 188). The ad-
dress is guaranteed to be valid on the trailing edge of
ALE. This pin is three-stated during ONCE mode. This
pin is not three-stated during a bus hold or reset.
AD15–AD8—On the Am186ES microcontroller, these
time-multiplexed pins supply memory or I/O addresses
and data to the system. This bus can supply an
address to the system during the first period of a bus
cycle (t1). It supplies data to the system during the
remaining periods of that cycle (t2, t3, and t4).
ARDY
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is deasserted, these pins are three-stated during
t2, t3, and t4.
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin is a true asynchronous ready that indicates to
the microcontroller that the addressed memory space
or I/O device will complete a data transfer. The ARDY
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
Am186/188ES and Am186/188ESLV Microcontrollers
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