P R E L I M I N A R Y
addition, it has weak internal pullup resistors that are
INT4/PIO30
active during reset.
Maskable Interrupt Request 4 (input,
asynchronous)
This signal functions like the corresponding signal in
the Am186EM and Am188EM microcontrollers except
that MCS0 can be programmed as the chip select for
the entire middle chip select address range.
This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT4 pin is not
masked, the microcontroller then transfers program
execution to the location specified by the INT4 vector in
the microcontroller interrupt vector table.
MCS2–MCS1
(MCS2/PIO24, MCS1/PIO15)
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee
interrupt recognition, the requesting device must
continue asserting INT4 until the request is
acknowledged.
Midrange Memory Chip Selects (output,
synchronous, internal pullup)
These pins indicate to the system that a memory
access is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. On the
Am186ES microcontroller, MCS2–MCS1 are
configured for 8-bit or 16-bit bus size by the auxiliary
configuration register. MCS2–MCS1 are held High
during a bus hold condition. In addition, they have weak
internal pullup resistors that are active during reset.
When pulse width demodulation mode is enabled, the
INT4 signal is used internally to indicate a High-to-Low
transition on the PWD signal. When pulse width
demodulation mode is enabled, INT4/PIO30 can be
used as a PIO.
LCS/ONCE0
These signals function like the signals in the Am186EM
and Am188EM microcontrollers except that if MCS0 is
programmed to be active for the entire middle chip-
select range, then these signals are available as PIOs.
Lower Memory Chip Select (output, synchronous,
internal pullup)
ONCE Mode Request 0 (input)
LCS—This pin indicates to the system that a memory
access is in progress to the lower memory block. The
base address and size of the lower memory block are
programmable up to 512 Kbytes. On the Am186ES
microcontroller, LCS is configured for 8-bit or 16-bit bus
size by the auxiliary configuration register. LCS is held
High during a bus hold condition.
If they are not programmed as PIOs and if MCS0 is
programmed for the whole middle chip-select range,
then these signals operate normally.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
ONCE0—During reset, this pin and ONCE1 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode; otherwise, it operates normally.
MCS3—This pin indicates to the system that a memory
access is in progress to the fourth region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. On the
Am186ES microcontroller, MCS3 is configured for 8-bit
or 16-bit bus size by the auxiliary configuration register.
MCS3 is held High during a bus hold condition. In
addition, this pin has a weak internal pullup resistor that
is active during reset.
In ONCE mode, all pins assume a high-impedance
state and remain in that state until a subsequent reset
occurs. To guarantee that the microcontroller does not
inadvertently enter ONCE mode, ONCE0 has a weak
internal pullup resistor that is active only during reset.
This pin is not three-stated during a bus hold condition.
This signal functions like the corresponding signal in
the Am186EM and Am188EM microcontrollers except
that if MCS0 is programmed for the entire middle chip-
select range, then this signal is available as a PIO. If
MCS3 is not programmed as a PIO and if MCS0 is
programmed for the entire middle chip-select range,
then this signal operates normally. Depending on the
chip configuration, this signal can serve as a memory
RFSH.
MCS0
(MCS0/PIO14)
Midrange Memory Chip Select 0 (output,
synchronous, internal pullup)
This pin indicates to the system that a memory access
is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. On the
Am186ES microcontroller, MCS0 is configured for 8-bit
or 16-bit bus size by the auxiliary configuration register.
MCS0 is held High during a bus hold condition. In
RFSH—This pin provides a signal timed for auto
refresh to PSRAM or DRAM devices. It is only enabled
to function as a refresh pulse when the PSRAM or
DRAM mode bit is set. An active Low pulse is
Am186/188ES and Am186/188ESLV Microcontrollers
31
AMD [ AMD ]
