Offset
(Hexadecimal)
FE
Register Name
Peripheral Control Block Relocation Register
w
w
w
w
F6
Reset Configuration Register
*
F4
Processor Release Level Register
F0
PDCON Register
E6
E4
E2
E0
Watchdog Timer Control Register
Enable RCU Register
**
Clock Prescaler Register
Memory Partition Register
w
w
DA
D8
DMA 1 Control Register
DMA 1 Transfer Count Register
D6
D4
D2
DMA 1 Destination Address High Register
DMA 1 Destination Address Low Register
DMA 1 Source Address High Register
DMA 1 Source Address Low Register
D0
CA
C8
C6
C4
C2
C0
DMA 0 Control Register
DMA 0 Transfer Count Register
DMA 0 Destination Address High Register
DMA 0 Destination Address Low Register
DMA 0 Source Address High Register
DMA 0 Source Address Low Register
w
w
AC
A8
A6
**
Internal Memory Chip Select Register
PCS and MCS Auxiliary Register
Note: Gaps in offset addresses
indicate reserved registers. No
accessshouldbemadetoreserved
registers.
Midrange Memory Chip Select Register
Peripheral Chip Select Register
A4
A2
A0
Changed from original Am186
microcontroller
Low Memory Chip Select Register
Upper Memory Chip Select Register
ChangedfromAm186EMand
Am188EM microcontrollers
w
w
*
88
86
84
Serial Port Baud Rate Divisor Register
Serial Port Receive Register
Serial Port Transmit Register
Serial Port Status Register
New to the Am186ER and
Am188ER microcontrollers
**
82
80
Serial Port Control Register
Figure 9. Peripheral Control Block Register Map
46
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
