WR
Table 6. Clocking Modes
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus
is to be written to a memory or I/O device. WR is three-
stated during a bus hold or reset condition.
CLKSEL2
CLKSEL1
Clocking Mode
Times Four
H
H
L
H
L
Divide by Two
Times One
X1
H
L
Crystal Input (input)
L
Reserved1
This pin and the X2 pin provide connections for a fun-
damental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER micro-
controllers, X1 is not 5-V tolerant and has a maximum
Notes:
1. The reserved clocking mode should not be used. Entering
the reserved clocking mode may cause unpredictable
system behavior.
input equal to VCC
.
V
CC
X2
Power Supply (input)
Crystal Output (output)
These pins supply power (+3.3 V) to the microcontrol-
ler.
This pin and the X1 pin provide connections for a fun-
damental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER micro-
controllers, X2 is not 5-V tolerant.
WHB (Am186™ER Microcontroller Only)
Write High Byte (output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a
write cycle. In 80C186 designs, this information is pro-
vided by BHE, AD0, and WR. However, by using WHB
and WLB, the standard system interface logic and ex-
ternal address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical
OR of BHE and WR. During reset, this pin is a pullup.
This pin is three-stated during bus holds and ONCE
mode.
WLB (Am186™ER Microcontroller Only)
WB (Am188™ER Microcontroller Only)
Write Low Byte (output, three-state, synchronous)
Write Byte (output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which
bytes of the data bus (upper, lower, or both) participate
in a write cycle. In 80C186 designs, this information is
provided by BHE, AD0, and WR. However, by using
WHB and WLB, the standard system interface logic
and external address latch that were required are elim-
inated.
WLB is asserted with AD7–AD0. WLB is the logical OR
of A0 and WR. This pin is three-stated during bus holds
and ONCE mode.
WB—On the Am188ER microcontroller, this pin indi-
cates a write to the bus. WB uses the same early timing
as the nonmultiplexed address bus. WB is associated
with AD7–AD0. This pin is three-stated during bus
holds and ONCE mode.
Am186TMER and Am188TMER Microcontrollers Data Sheet
39
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