If the code crashes or hangs, the TIMER1 countdown
will cause a watchdog interrupt.
The WDT can be configured to cause either an NMI in-
terrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON
Register is set when the NMI is generated. The NMI in-
terrupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
by an external source. If the NMIFLAG is set, the ISR
should clear the flag by writing the correct keyed se-
quence to the WDTCON Register. If the NMIFLAG is
set when a second WDT timeout occurs, a WDT sys-
tem reset is generated rather than a second NMI event.
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a prescale to timers 0 and 1, or
as a DMA request source.
The timers are controlled by eleven 16-bit registers in
the peripheral control block. A timer’s timer-count reg-
ister contains the current value of that timer. The timer-
count register can be read or written with a value at any
time, whether the timer is running or not. The microcon-
troller increments the value of the timer-count register
each time a timer event occurs.
When the processor takes a WDT reset, either be-
cause of a single WDT event with the WDT configured
to generate resets or due to a WDT event with the NMI-
FLAG set, the RSTFLAG in the WDTCON Register is
set. This allows system initialization code to differenti-
ate between a hardware reset and a WDT reset and
take appropriate action. The RSTFLAG is cleared
when the WDTCON Register is read or written. The
processor does not resample external pins during a
WDT reset. This means that the clocking, the Reset
Configuration Register, and any other features that are
user-selectable during reset do not change when a
WDT system reset occurs. PIO Mode and PIO Direc-
tion registers are not affected and PIO data is unde-
fined. All other activities are identical to those of a
normal system reset.
Each timer also has a maximum-count register that de-
fines the maximum value the timer will reach. When the
timer reaches the maximum value, it resets to 0 during
the same clock cycle—the value in the maximum-count
register is never stored in the timer-count register. Also,
timers 0 and 1 have a secondary maximum-count reg-
ister. Using both the primary and secondary maximum-
count registers lets the timer alternate between two
maximum values.
If the timer is programmed to use only the primary max-
imum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is reached.
If the timer is programmed to use both of its maximum-
count registers, the output pin indicates which maxi-
mum-count register is currently in control, thereby cre-
ating a waveform. The duty cycle of the waveform
depends on the values in the maximum-count regis-
ters.
Note: The Watchdog Timer (WDT) is inactive after
reset.
DIRECT MEMORY ACCESS
Direct memory access (DMA) permits transfer of data
between memory and peripherals without CPU involve-
ment. The DMA unit in the Am186ER and Am188ER
microcontrollers, shown in Figure 13, provides two
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., memory to I/O)
or within the same space (e.g., memory-to-memory or
I/O-to-I/O). Additionally, bytes (also words on the
Am186ER microcontroller) can be transferred to or
from even or odd addresses. Only two bus cycles (a
minimum of eight clocks) are necessary for each data
transfer.
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter the
internal clock frequency. A timer can be clocked exter-
nally at this same frequency; however, because of in-
ternal synchronization and pipelining of the timer
circuitry, the timer output may take up to six clock cy-
cles to respond to the clock or gate input.
WATCHDOG TIMER
The Am186ER/Am188ER microcontrollers provide a
hardware watchdog timer. The Watchdog Timer (WDT)
can be used to regain control of the system when soft-
ware fails to respond as expected. The WDT is inactive
after reset. It can be modified only once by a keyed se-
quence of writes to the Watchdog Timer Control Regis-
ter (WDTCON) following reset. This single write can
either disable the timer or modify the timeout period
and the action taken upon timeout. A keyed sequence
is also required to reset the current WDT count. This
behavior ensures that randomly executing code will not
prevent a WDT event from occurring.
Each channel accepts a DMA request from one of the
four sources: the channel request pin (DRQ1–DRQ0),
Timer 2, a serial port, or system software. The two
DMA channels can be programmed with different prior-
ities to resolve simultaneous DMA requests, and trans-
fers on one channel can interrupt the other channel.
The DMA channels can be directly connected to the
asynchronous serial port. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a data source in memory or
I/O space and a serial port transmit or receive register.
The WDT supports up to a 1.34-second timeout period
in a 50-MHz system.
54
Am186TMER and Am188TMER Microcontrollers Data Sheet
AMD [ AMD ]
