Offset
Register Name
(Hexadecimal)
w
w
PIO Data 1 Register
7A
78
76
74
72
70
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
PIO Direction 0 Register
PIO Mode 0 Register
w
w
Timer 2 Mode/Control Register
66
62
60
5E
5C
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
5A
58
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
56
54
52
50
w
w
Serial Port Interrupt Control Register
44
42
40
3E
Watchdog Timer Interrupt Control Register
INT4 Control Register
INT3 Control Register
INT2 Control Register
INT1 Control Register
3C
3A
38
INT0 Control Register
DMA 1 Interrupt Control Register
DMA 0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
36
34
32
30
2E
2C
2A
Priority Mask Register
Interrupt Mask Register
Poll Status Register
28
26
Poll Register
24
22
End-of-Interrupt Register
Notes: Gaps in offset addresses
indicate reserved registers. No
access should be made to reserved
registers.
Interrupt Vector Register
20
18
16
14
12
10
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Transmit 1 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Changed from original Am186
microcontroller
Figure 9. Peripheral Control Block Register Map (Continued)
Am186TMER and Am188TMER Microcontrollers Data Sheet
47
AMD [ AMD ]
