P R E L I M I N A R Y
Interrupt Acknowledge Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
A19–A0
S6
68
Address
7
8
S6
S6
1
(b)
2
AD15–AD0*,
AD7–AD0**
12
15
Ptr
AO15–AO8**
Address
23
9
ALE
10
11
BHE
BHE*
31
21
INTA1–INTA0
DEN
20
(c)
19
3
22
22
DT/R
(d)
(a)
4
22
Status
S2–S0
Notes:
*
Am186EM microcontroller only
Am188EM microcontroller only
**
a The status bits become inactive in the state preceding t4.
b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c This parameter applies for an interrupt acknowledge cycle that follows a write cycle.
d If followed by a write cycle, this change occurs in the state preceding that write cycle.
80
Am186/188EM and Am186/188EMLV Microcontrollers