P R E L I M I N A R Y
falling edge of ARDY must be synchronized to CLK-
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data, regardless of the
DA bit setting. This pin is sampled on the rising edge of
RES. (S6 and UZI also assume their normal functional-
ity in this instance. See Table 2 on page 30.)
OUTA. To always assert the ready condition to the mi-
crocontroller, tie ARDY High. If the system does not
use ARDY, tie the pin Low to yield control to SRDY.
BHE/ADEN
(Am186EM Microcontroller Only)
Note: On the Am188EM microcontroller, AO15–AO8
are driven during the entire bus cycle, regardless of the
setting of the DA bit in the UMCS and LMCS registers.
Bus High Enable (three-state, output, synchronous)
Address Enable (input, internal pullup)
CLKOUTA
BHE—During a memory access, this pin and the least-
significant address bit (AD0 or A0) indicate to the sys-
tem which bytes of the data bus (upper, lower, or both)
participate in a bus cycle. The BHE/ADEN and AD0
pins are encoded as shown in Table 1.
Clock Output A (output, synchronous)
This pin supplies the internal clock to the system. De-
pending on the value of the power-save control register
(PDCON), CLKOUTA operates at either the crystal
input frequency (X1), the power-save frequency, or is
three-stated. CLKOUTA remains active during reset
and bus hold conditions.
BHE is asserted during t1 and remains asserted
through t3 and tW. BHE does not need to be latched.
BHE floats during bus hold and reset.
CLKOUTB
On the Am186EM and Am188EM microcontrollers,
WLB and WHB implement the functionality of BHE and
AD0 for high and low byte write enables.
Clock Output B (output, synchronous)
This pin supplies an additional clock to the system. De-
pending upon the value of the power-save control reg-
ister (PDCON), CLKOUTB operates at either the
crystal input frequency (X1), the power-save fre-
quency, or is three-stated. CLKOUTB remains active
during reset and bus hold conditions.
Table 1. Data Byte Encoding
BHE AD0 Type of Bus Cycle
0
0
1
1
0
1
0
1
Word Transfer
DEN/PIO5
High Byte Transfer (Bits 15–8)
Low Byte Transfer (Bits 7–0)
Refresh
Data Enable (output, three-state, synchronous)
This pin supplies an output enable to an external data-
bus transceiver. DEN is asserted during memory, I/O,
and interrupt acknowledge cycles. DEN is deasserted
when DT/R changes state. DEN floats during a bus hold
or reset condition.
BHE/ADEN also signals DRAM refresh cycles when
using the multiplexed address and data (AD) bus. A re-
fresh cycle is indicated when both BHE/ADEN and AD0
are High. During refresh cycles, the A bus and the AD
bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this
reason, the A0 signal cannot be used in place of the
AD0 signal to determine refresh cycles. PSRAM re-
freshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description on page 28).
DRQ1–DRQ0
(DRQ1/PIO13, DRQ0/PIO12)
DMA Requests (input, synchronous,
level-sensitive)
These pins indicate to the microcontroller that an exter-
nal device is ready for DMA channel 1 or channel 0 to
perform a transfer. DRQ1–DRQ0 are level-triggered
and internally synchronized.
The DRQ signals are not latched and must remain ac-
tive until serviced.
ADEN—If BHE/ADEN is held High or left floating dur-
ing power-on reset, the address portion of the AD bus
(AD15–AD0 for the 186 or AO15–AO8 and AD7–AD0
for the 188) is enabled or disabled during LCS and
UCS bus cycles based on the DA bit in the LMCS and
UMCS registers. If the DA bit is set, the memory ad-
dress is accessed on the A19–A0 pins. There is a weak
internal pullup resistor on BHE/ADEN so no external
pullup is required. This mode of operation reduces
power consumption.
DT/R/PIO4
Data Transmit or Receive (output, three-state,
synchronous)
This pin indicates which direction data should flow
through an external data-bus transceiver. When DT/R
is asserted High, the microcontroller transmits data. When
this pin is deasserted Low, the microcontroller receives
data. DT/R floats during a bus hold or reset condition.
26
Am186/188EM and Am186/188EMLV Microcontrollers
AMD [ AMD ]
