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AM186ES-40KI/W 参数 Datasheet PDF下载

AM186ES-40KI/W图片预览
型号: AM186ES-40KI/W
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能, 80C186- / 80C188兼容和80L186- / 80L188兼容的16位嵌入式微控制器 [High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 102 页 / 1514 K
品牌: AMD [ AMD ]
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P R E L I M I N A R Y  
the defaults for the PIOs. The system initialization code  
PROGRAMMABLE I/O (PIO) PINS  
must reconfigure the PIOs as required.  
There are 32 pins on the Am186ES and Am188ES mi-  
crocontrollers that are available as user-programmable  
I/O signals. Table 2 on page 34 and Table 3 on  
page 34 list the PIO pins. Each of these pins can be  
used as a user-programmable input or output signal if  
the normal shared function is not needed.  
The A19–A17 address pins default to normal operation  
on power-on reset, allowing the processor to correctly  
begin fetching instructions at the boot address  
FFFF0h. The DT/R, DEN, and SRDY pins also default  
to normal operation on power-on reset.  
If a pin is enabled to function as a PIO signal, the pre-  
assigned signal function is disabled and does not affect  
the level on the pin. A PIO signal can be configured to  
operate as an input or output with or without a weak  
pullup or pulldown, or as an open-drain output.  
Note that emulators use A19, A18, A17, S6, and UZI.  
In environments where an emulator is needed, these  
pins must be configured for normal function—not as  
PIOs.  
If the AD15–AD0 bus override is enabled on power-on  
reset, then S6/CLKDIV2 and UZI revert to normal oper-  
ation instead of PIO input with pullup. If BHE/ADEN  
(186) or RFSH2/ADEN (188) is held Low during power-  
on reset, the AD15–AD0 bus override is enabled.  
After power-on reset, the PIO pins default to various  
configurations. The column titled Power-On Reset Sta-  
tus in Table 2 on page 34 and Table 3 on page 34 lists  
52  
Am186/188ES and Am186/188ESLV Microcontrollers  
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