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AM186ES-40KI/W 参数 Datasheet PDF下载

AM186ES-40KI/W图片预览
型号: AM186ES-40KI/W
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能, 80C186- / 80C188兼容和80L186- / 80L188兼容的16位嵌入式微控制器 [High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 102 页 / 1514 K
品牌: AMD [ AMD ]
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P R E L I M I N A R Y  
PULSE WIDTH DEMODULATION  
ASYNCHRONOUS SERIAL PORTS  
For many applications, such as bar-code reading, it is  
necessary to measure the width of a signal in both its  
High and Low phases. The Am186ES and Am188ES  
microcontrollers provide a pulse-width demodulation  
(PWD) option to fulfill this need. The PWD bit in the  
system configuration register (SYSCON) enables the  
PWD option. Please note that the Am186ES and  
Am188ES microcontrollers do not support analog-to-  
digital conversion.  
The Am186ES and Am188ES microcontrollers provide  
two independent asynchronous serial ports. These  
ports provide full-duplex, bidirectional data transfer  
using several industry-standard communications pro-  
tocols. The serial ports can be used as sources or des-  
tinations of DMA transfers.  
The asynchronous serial ports support the following  
features:  
n Full-duplex operation  
n 7-bit, 8-bit, or 9-bit data transfers  
n Odd, even, or no parity  
n One stop bit  
In PWD mode, TMRIN0, TMRIN1, INT2, and INT4 are  
configured internal to the microcontroller to support the  
detection of rising and falling edges on the PWD input  
pin (INT2/INTA0/PWD) and to enable either timer 0  
when the signal is High or timer 1 when the signal is  
Low. The INT4, TMRIN0, and TMRIN1 pins are not  
used in PWD mode and so are available for use as  
PIOs.  
n Two lengths of break characters  
n Error detection  
— Parity errors  
The following diagram shows the behavior of a system  
for a typical waveform.  
— Framing errors  
— Overrun errors  
n Hardware handshaking with the following select-  
able control signals:  
— Clear-to-send (CTS)  
INT4  
INT2 Ints generated  
TMR1 enabled  
— Enable-receiver-request (ENRX)  
— Ready-to-send (RTS)  
INT2  
TMR0 enabled  
— Ready-to-receive (RTR)  
n DMA to and from the serial ports  
The interrupt service routine (ISR) for the INT2 and  
INT4 interrupts should examine the current count of the  
associated timer, timer 1 for INT2 and timer 0 for INT4,  
in order to determine the pulse width. The ISR should  
then reset the timer count register in preparation for the  
next pulse.  
n Separate maskable interrupts for each port  
n Multidrop protocol (9-bit) support  
n Independent baud rate generators  
n Maximum baud rate of 1/16th of the CPU clock  
n Double-buffered transmit and receive  
Since the timers count at one quarter of the processor  
clock rate, this determines the maximum resolution that  
can be obtained. Further, in applications where the  
pulse width may be short, it may be necessary to poll  
the INT2 and INT4 request bits in the interrupt request  
register in order to avoid the overhead involved in tak-  
ing and returning from an interrupt. Overflow condi-  
tions, where the pulse width is greater than the  
maximum count of the timer, can be detected by mon-  
itoring the Maximum Count (MC) bit in the associated  
timer or by setting the INT bit to enable timer interrupt  
requests.  
DMA Transfers through the Serial Port  
The Am186ES and Am188ES microcontrollers support  
DMA transfers both to and from the serial port. Either  
or both DMA channels and either or both serial ports  
can be used for DMA transmits or receives. See the  
DMA Control register descriptions in the Am186ES and  
Am188ES Microcontrollers User’s Manual for more in-  
formation.  
Am186/188ES and Am186/188ESLV Microcontrollers  
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