P R E L I M I N A R Y
effect on the priority resolution of maskable interrupt re-
dress bit 1 to the system. During a bus hold condition,
A1 retains its previously latched value.
quests. For this reason, it is strongly advised that the
interrupt service routine for NMI does not enable the
maskable interrupts.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
An NMI transition from Low to High is latched and syn-
chronized internally, and it initiates the interrupt at the
next instruction boundary. To guarantee that the inter-
rupt is recognized, the NMI pin must be asserted for at
least one CLKOUTA period.
PCS6—This pin indicates to the system that a memory
access is in progress to the seventh region of the pe-
ripheral memory block (either I/O or memory address
space). The base address of the peripheral memory
block is programmable. PCS6 is held High during a bus
hold condition or reset.
PCS3–PCS0
(PCS3/PIO19, PCS2/PIO18,
PCS1/PIO17, PCS0/PIO16)
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory ac-
cess is in progress to the corresponding region of the
peripheral memory block (either I/O or memory ad-
dress space). The base address of the peripheral
memory block is programmable. PCS3–PCS0 are held
High during a bus hold condition. They are also held
High during reset.
A2—When the EX bit in the MCS and PCS Auxiliary
Register is 0, this pin supplies an internally latched ad-
dress bit 2 to the system. During a bus hold condition,
A2 retains its previously latched value.
PCS4 is not available on the Am186EM and Am188EM
microcontrollers.
PIO31–PIO0 (Shared)
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-byte
address range, which is twice the address range cov-
ered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186EM and Am188EM microcontrollers pro-
vide 32 individually programmable I/O pins. Each PIO
can be programmed with the following attributes: PIO
function (enabled/disabled), direction (input/output),
and weak pullup or pulldown.
PCS5/A1/PIO3
The pins that are multiplexed with PIO31–PIO0 are
listed in Table 2 and Table 3.
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS5—This pin indicates to the system that a memory
access is in progress to the sixth region of the periph-
eral memory block (either I/O or memory address
space). The base address of the peripheral memory
block is programmable. PCS5 is held High during a bus
hold condition. It is also held High during reset.
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset Sta-
tus in Table 2 and Table 3 lists the defaults for the PIOs. The
system initialization code must reconfigure any PIOs as
required.
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default to
normal operation on power-on reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asserts over a 256-
byte address range, which is twice the address range
covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched ad-
Am186/188EM and Am186/188EMLV Microcontrollers
29
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