P R E L I M I N A R Y
GND
INT1/SELECT
Ground
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
The ground pins connect the system ground to the mi-
crocontroller.
INT1—This pin indicates to the microcontroller that an
interrupt request has occurred. If INT1 is not masked,
the microcontroller transfers program execution to the
location specified by the INT1 vector in the microcon-
troller interrupt vector table.
HLDA
Bus Hold Acknowledge (output, synchronous)
This pin is asserted High to indicate to an external bus
master that the microcontroller has released control of
the local bus. When an external bus master requests
control of the local bus (by asserting HOLD), the micro-
controller completes the bus cycle in progress and then
relinquishes control of the bus to the external bus mas-
ter by asserting HLDA and floating DEN, RD, WR, S2–
S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and
DT/R, and then driving the chip selects UCS, LCS,
MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT1 until the request is acknowledged.
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external interrupt con-
troller, this pin indicates to the microcontroller that an
interrupt type appears on the address and data bus.
The INT0 pin must indicate to the microcontroller that
an interrupt has occurred before the SELECT pin indi-
cates to the microcontroller that the interrupt type ap-
pears on the bus.
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (i.e. for
refresh), it will deassert HLDA before the external bus
master deasserts HOLD. The external bus master
must be able to deassert HOLD and allow the micro-
controller access to the bus. See the timing diagrams
for bus hold on page 92.
INT2/INTA0/PIO31
Maskable Interrupt Request 2 (input,
asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
INT2—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT2 pin is not
masked, the microcontroller transfers program execu-
tion to the location specified by the INT2 vector in the
microcontroller interrupt vector table.
HOLD
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT2 until the request is acknowledged.
INT2 becomes INTA0 when INT0 is configured in cas-
cade mode.
The Am186EM and Am188EM microcontrollers’ HOLD
latency time is a function of the activity occurring in the
processor when the HOLD request is received. A
DRAM request will delay a HOLD request when both
requests are made at the same time. In addition, if
locked transfers are performed, the HOLD latency time
is increased by the length of the locked transfer.
INTA0—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT0. The periph-
eral issuing the interrupt request must provide the mi-
crocontroller with the corresponding interrupt type.
For more information, see the HLDA pin description.
INT0
Maskable Interrupt Request 0 (input,
asynchronous)
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
This pin indicates to the microcontroller that an inter-
rupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program execu-
tion to the location specified by the INT0 vector in the
microcontroller interrupt vector table.
INT3—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program ex-
ecution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee in-
terrupt recognition, the requesting device must con-
tinue asserting INT0 until the request is acknowledged.
Am186/188EM and Am186/188EMLV Microcontrollers
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AMD [ AMD ]
