P R E L I M I N A R Y
the processor to hang with the appearance of waiting
Low Memory Chip Select
for a ready signal. This behavior may occur even in a
system in which ready is always asserted (ARDY or
SRDY tied High).
The Am186ED/EDLV microcontrollers provide an LCS
chip select for lower memory. The AUXCON register
can be used to configure LCS for 8-bit or 16-bit ac-
cesses. Since the interrupt vector table is located at the
bottom of memory starting at 00000h, the LCS pin is
usually used to control data memory. The LCS pin is
not active on reset.
Configuring PCS in I/O space with LCS or any other
chip select configured for memory address 0 is not con-
sidered overlapping of the chip selects. Overlapping
chip selects refers to configurations where more than
one chip select asserts for the same physical address.
The LCS signal is multiplexed with the RAS0 signal
when the DRAM mode is enabled in the LMCS register.
The PCS can overlap DRAM blocks with different wait
states and without external or internal bus contention.
The RAS will assert along with the appropriate PCS.
The UCAS and LCAS will not assert, preventing the
DRAM from writing erroneously or driving the data bus
during a read. The PCS must have the same or higher
number of wait states than the DRAM. The PCS bus
width will be determined by the LSIZ or USIZ bus
widths. This will make a 1785-byte block of the DRAM
inaccessible. In its place, the peripherals associated
with the PCS can be accessed. This is especially use-
ful when the entire memory space is used with two
banks of DRAM or a bank of DRAM and a 512K Flash.
Midrange Memory Chip Selects
The Am186ED/EDLV microcontrollers provide four
chip selects, MCS3–MCS0, for use in a user-locatable
memory block. With some exceptions, the base ad-
dress of the memory block can be located anywhere
within the 1-Mbyte memory address space. The areas
associated with the UCS and LCS chip selects are ex-
cluded. If they are mapped to memory, the address
range of the peripheral chip selects, PCS6, PCS5, and
PCS3–PCS0, are also excluded. The MCS address
range can overlap the PCS address range if the PCS
chip selects are mapped to I/O space.
Upper Memory Chip Select
MCS0 can be configured to be asserted for the entire
MCS range. When configured in this mode, the MCS3–
MCS1 pins can be used as PIOs or DRAM control sig-
nals.
The Am186ED/EDLV microcontrollers provide a UCS
chip select for the top of memory. On reset the
Am186ED/EDLV microcontrollers begin fetching and
executing instructions at memory location FFFF0h.
Therefore, upper memory is usually used as instruction
memory. To facilitate this usage, UCS defaults to active
on reset, with a default memory range of 64 Kbytes
from F0000h to FFFFFh, with external ready required
and three wait states automatically inserted. The UCS
memory range always ends at FFFFFh. The UCS
lower boundary is programmable.
The AUXCON register can be used to configure MCS
for 8-bit or 16-bit accesses. The bus width of the MCS
range is determined by the width of the non-UCS/non-
LCS memory range.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the same timing as the multiplexed AD ad-
dress bus.
The bus width associated with UCS is determined on
reset by the S2/BTSEL. If S2/BTSEL is pulled High or
left floating, an internal pullup sets the boot mode op-
tion to 16-bit. If S2/BTSEL is pulled resistively Low dur-
ing reset, the boot mode option is for 8-bit. The status
of the S2/BTSEL pin is latched on the rising edge of re-
set. If 8-bit mode is selected, the width of the memory
region associated with UCS can be changed in the
AUXCON register. If UCS boots as a 16-bit space, it is
not re-configurable to 8-bit. This allows for cheaper 8-
bit-wide memory to be used for booting the Am186ED/
EDLV microcontrollers, while speed-critical code and
data can be executed from 16-bit-wide lower memory.
Eight-bit or 16-bit-wide peripherals can be used in the
memory area between LCS and UCS or in the I/O
space. The entire memory map can be set to 16-bit or
8-bit or mixed between 8-bit and 16-bit based on the
USIZ, LSIZ, MSIZ, and IOSIZ bits in the AUXCON reg-
ister.
Activating either bank of DRAM will change the MCS1
and MCS2 functionality to UCAS and LCAS. Activating
the upper DRAM bank will change the MCS3 function-
ality to RAS1. It is recommended that when either bank
of DRAM is activated, either MCS0 be configured to as-
sert for the entire MCS range or that MCS space be un-
used. If the lower bank of DRAM is activated, but not
the upper bank of DRAM, MCS3 can still be used as a
chip select or PIO. The MCS2 and MCS1 portion of the
middle chip select address space will not have a chip
select signal asserted, but the wait states will still be
valid.
Peripheral Chip Selects
The Am186ED/EDLV microcontrollers provide six chip
selects, PCS6–PCS5 and PCS3–PCS0, for use within
a user-configured memory or I/O block. PCS4 is not
available on the Am186ED/EDLV microcontrollers. The
base address of the memory block can be located any-
where within the 1-Mbyte memory address space, ex-
clusive of the areas associated with the UCS, LCS, and
Am186ED/EDLV Microcontrollers
43
AMD [ AMD ]
