P R E L I M I N A R Y
Am186ED/EDLV MICROCONTROLLERS BLOCK DIAGRAM
INT2/INTA0/PWD**
INT3/INTA1/IRQ
INT6–INT4**
INT1/SELECT
INT0
CLKOUTA
TMROUT0 TMROUT1
PWD**
TMRIN0
TMRIN1
DRQ0/INT5** DRQ1/INT6**
CLKOUTB
NMI
Timer Control
Unit
DMA
Unit
X2
X1
Pulse
0
1
Max Count B
Registers
2
0
1
Width
Demod-
ulator
Clock and
Power
Management
Unit
V
CC
20-Bit Source
Pointers
20-Bit Destination
Interrupt
Control Unit
GND
Max Count A
Registers
(PWD)
Pointers
Watchdog
16-Bit Count
16-Bit Count
Timer (WDT)
Control
Registers
Control
Registers
Control
Control
Registers
Registers
Registers
Registers
PIO
Unit
PIO31–
PIO0*
RES
Control
Control
Control
Refresh
DRAM
Registers
Registers
Registers
Control
Unit
Control
Unit
ARDY
TXD0
SRDY
S2/BTSEL
S1–S0
RXD0
Asynchronous
Serial Port 0
RTS0/RTR0
CTS0/ENRX0
Bus
Interface
Unit
DT/R
Chip-Select
Unit
Execution
Unit
DEN/DS
HOLD
TXD1
RXD1
Asynchronous
Serial Port 1
HLDA
RTS1/RTR1**
CTS1/ENRX1**
S6/CLKDIV2
UZI
RD
WHB
WLB
LCS/ONCE0/RAS0
MCS3/RAS1
PCS6/A2
PCS5/A1
A19–A0
AD15–AD0
MCS2/LCAS
PCS3–PCS0**
UCS/ONCE1
WR
BHE/ADEN
MCS1/UCAS
MCS0
ALE
Notes:
*All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 21 and Table 2 on page 29 for
information on shared functions.
** RTS1/RTR1 and CTS1/ENRX1 are multiplexed with PCS3 and PCS2, respectively. See the pin descriptions beginning on
page 21.
2
Am186ED/EDLV Microcontrollers
AMD [ AMD ]
