P R E L I M I N A R Y
COMPARING THE Am186ES/ESLV TO THE Am186ED/EDLV MICROCONTROLLERS
Compared to the Am186ES/ESLV microcontrollers, the
Am186ED/EDLV microcontrollers have the following
additional features:
significantly better performance with its 40-MHz clock
rate.
Integrated DRAM Controller
n Integrated DRAM controller
n Enhanced refresh control unit
The integrated DRAM controller directly interfaces
DRAM to support no-wait state DRAM interface up to
40 MHz. Wait states can be inserted to support slower
DRAM. All signals required by the DRAM are
generated on the Am186ED/EDLV microcontrollers
and no external logic is required. The DRAM
multiplexed address pins are connected to the odd
address pins starting with A1 on the Am186ED/EDLV
microcontrollers to MA0 on the DRAM. The correct row
and column addresses are generated on these pins
during a DRAM access. The UCAS and LCAS are used
to select which byte of the DRAM is accessed during a
read or write. The RAS0 controls the lower bank of
DRAM which starts at 00000h in the address map and
is bounded by the lower memory size selected in the
LMCS register. RAS1 controls the upper bank of
DRAM which ends at FFFFFh and is bounded by the
upper memory size in the UMCS register. When RAS1
is enabled, UCS is automatically disabled. Neither,
either, or both DRAM banks can be activated.
n Option to overlap DRAM with peripheral chip select
(PCS)
n Additional serial port mode for DMA support of 9-bit
protocols
n Option to boot from 8- or 16-bit memory
n Improved external bus master support
n PSRAM controller removed
Figure 1 shows an example system using a 40-MHz
Am186ED microcontroller. Figure 2 shows a
comparable system implementation with an 80C186.
Because of its superior integration, the Am186ED/
EDLV system does not require the support devices that
are required on the 80C186 example system. In
addition, the Am186ED/EDLV microcontrollers provide
25
Figure 2. 80C186 Microcontroller Example System Design
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Am186ED/EDLV Microcontrollers
AMD [ AMD ]
