P R E L I M I N A R Y
t1
t2
t3
Data
Phase
t4
Address
Phase
CLKOUTA
A19–A0
Address
AD15–AD0
(Read)
Data
AD15–AD0
(Write)
Data
LCS, or UCS
or
MCSx, PCSx
Note: For a detailed description of DRAM control signals, see DRAM switching characteristics
beginning on page 70.
Figure 5. 16-Bit Mode—Read and Write with Address Bus Disable In Effect
t1
t2
t3
t4
Address
Phase
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Address
Data
AD15–AD8
(Read or Write)
Address
AD7–AD0
(Write)
Address
Data
LCS or UCS
or
MCSx, PCSx
Figure 6. 8-Bit Mode—Normal Read and Write Operation
Am186ED/EDLV Microcontrollers
35