P R E L I M I N A R Y
not drive the address during t1. There is a weak internal
ARDY
pullup resistor on BHE/ADEN so no external pullup is
required. Disabling the address phase reduces power
consumption.
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin is a true asynchronous ready that indicates to
the microcontroller that the addressed memory space
or I/O device will complete a data transfer. The ARDY
pin is asynchronous to CLKOUTA and is active High.
To guarantee the number of wait states inserted, ARDY
or SRDY must be synchronized to CLKOUTA. If the
falling edge of ARDY is not synchronized to CLKOUTA
as specified, an additional clock period can be added.
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data, regardless of the
DA bit setting. The pin is sampled on the rising edge of
RES. (S6 and UZI also assume their normal
functionality in this instance. See Table 2 on page 29.)
The internal pullup on ADEN is ~9 kohm.
Note: For 8-bit accesses, AD15–AD8 are driven with
addresses during the t2–t4 bus cycle, regardless of the
setting of the DA bit in the UMCS and LMCS registers.
To always assert the ready condition to the
microcontroller, tie ARDY High. If the system does not
use ARDY, tie the pin Low to yield control to SRDY.
CLKOUTA
Clock Output A (output, synchronous)
BHE/ADEN
This pin supplies the internal clock to the system.
Depending on the value of the system configuration
register (SYSCON), CLKOUTA operates at either the
PLL frequency (X1), the power-save frequency, or is
held Low. CLKOUTA remains active during reset and
bus hold conditions.
Bus High Enable (three-state, output,
synchronous)
Address Enable (input, internal pullup)
BHE—During a memory access, this pin and the least-
significant address bit (AD0 or A0) indicate to the
system which bytes of the data bus (upper, lower, or
both) participate in a bus cycle. The BHE/ADEN and
AD0 pins are encoded as shown in Table 1.
All AC timing specs that use a clock relate to
CLKOUTA.
CLKOUTB
Table 1. Data Byte Encoding
Clock Output B (output, synchronous)
This pin supplies an additional clock with a delayed
output compared to CLKOUTA. Depending upon the
value of the system configuration register (SYSCON),
CLKOUTB operates at either the PLL frequency (X1),
the power-save frequency, or is held Low. CLKOUTB
remains active during reset and bus hold conditions.
BHE AD0
Type of Bus Cycle
Word Transfer
0
0
1
1
0
1
0
1
High Byte Transfer (Bits 15–8)
Low Byte Transfer (Bits 7–0)
Reserved
CLKOUTB is not used for AC timing specs.
BHE is asserted during t1 and remains asserted
through t3 and tW. BHE does not need to be latched.
BHE floats during bus hold and reset.
CTS0/ENRX0/PIO21
Clear-to-Send 0 (input, asynchronous)
Enable-Receiver-Request 0 (input, asynchronous)
WLB and WHB implement the functionality of BHE and
AD0 for High and Low byte-write enables. UCAS and
LCAS implement High and Low-byte selection for
DRAM devices.
CTS0—This pin provides the Clear-to-Send signal for
asynchronous serial port 0 when the ENRX0 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The CTS0 signal gates the
transmission of data from the associated serial port
transmit register. When CTS0 is asserted, the
transmitter begins transmission of a frame of data, if
any is available. If CTS0 is deasserted, the transmitter
holds the data in the serial port transmit register. The
value of CTS0 is checked only at the beginning of the
transmission of the frame.
BHE/ADEN also signals DRAM refresh cycles when
using the multiplexed address and data (AD) bus. A
refresh cycle is indicated when both BHE/ADEN and
AD0 are High. During refresh cycles, the A bus is
indeterminate and the AD bus is driven to FFFFh
during the address phase of the AD bus cycle. For this
reason, the A0 signal cannot be used in place of the
AD0 signal to determine refresh cycles.
ADEN—If BHE/ADEN is held High or left floating
during power-on reset, the address portion of the AD
bus (AD15–AD0) is enabled or disabled during LCS
and UCS bus cycles based on the DA bit in the LMCS
and UMCS registers. If the DA bit is set, the AD bus will
ENRX0—This pin provides the Enable Receiver
Request for asynchronous serial port 0 when the
ENRX0 bit in the AUXCON register is 1 and hardware
flow control is enabled for the port (FC bit in the serial
22
Am186ED/EDLV Microcontrollers
AMD [ AMD ]
