P R E L I M I N A R Y
n Enhanced performance—The Am186ED/EDLV
Clock Generation
microcontrollers increase the performance of
80C186/188 systems, and the nonmultiplexed ad-
dress bus offers unbuffered access to memory.
The integrated clock generation circuitry of the
Am186ED/EDLV microcontrollers enables the use of a
1x crystal frequency. The Am186ED design in Figure 1
achieves 40-MHz CPU operation, while using a 40-
MHz crystal.
n Enhanced functionality—The enhanced on-chip
peripherals of the Am186ED/EDLV microcontrollers
include two asynchronous serial ports, 32 PIOs, a
watchdog timer, additional interrupt pins, a pulse
width demodulation option, DMA directly to and from
the serial ports, 8-bit and 16-bit programmable bus
sizing, a 16-bit reset configuration register, and en-
hanced chip-select functionality.
Application Considerations
The integration enhancements of the Am186ED/EDLV
microcontrollers provide a high-performance, low-sys-
tem-cost solution for 16-bit embedded microcontroller
designs. The nonmultiplexed address bus eliminates
the need for system-support logic to interface memory
devices, while the multiplexed address/data bus main-
tains the value of previously engineered, customer-
specific peripherals and circuits within the upgraded
design.
Figure 1 illustrates an example system design that
uses the integrated peripheral set to achieve high per-
formance with reduced system cost.
Memory Interface
0-6
The Am186ED/EDLV microcontrollers integrate a ver-
satile memory controller which supports direct memory
accesses to DRAM, SRAM, Flash, EPROM, and ROM.
No external glue logic is required and all required con-
trol signals are provided. The peripheral chip selects
have been enhanced to allow them to overlap the
DRAM. This allows a small 1.5K portion of the DRAM
memory space to be used for peripherals without bus
contention.
Figure 1. Am186ED Microcontroller Example
System Design
Direct Memory Interface Example
Figure 1 illustrates the direct memory interface of the
Am186ED microcontroller. The processor’s A19–A0
bus connects to the memory address inputs, the AD
bus connects to the data inputs and outputs, and the
chip selects connect to the memory chip-select inputs.
The odd A1–A17 address pins connect to the DRAM
multiplexed address bus.
The improved memory timing specifications of the
Am186ED/EDLV microcontrollers allow for zero-wait-
state operation at 40 MHz using 50-ns DRAM, 70-ns
SRAM, or 70-ns Flash memory. For 60-ns DRAM one
wait state is required at 40 MHz and zero wait states at
33 MHz and below. For 70-ns DRAM two wait states
are required at 40 MHz, one wait state at 33 MHz, and
zero wait states at 25 MHz and below. This reduces
overall system cost by enabling the use of commonly
available memory speeds and taking advantage of
DRAM’s lower cost per bit over SRAM.
The RD output connects to the DRAM Output Enable
(OE) pin for read operations. Write operations use the
WR output connected to the DRAM Write Enable (WE)
pin. The UCAS and LCAS pins provide byte selection.
Figure 1 also shows an implementation of an RS-232
console or modem communications port. The RS-232
to CMOS voltage-level converter is required for the
electrical interface with the external device.
Am186ED/EDLV Microcontrollers
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