D A T A S H E E T
Refer to the Table 10 on page 28 for RESET# parame-
Output Disable Mode
When the OE# input is at V , output from the device is
disabled. The output pins are placed in the high imped-
ance state.
ters and to Figure 14, on page 29 for the timing
diagram.
IH
Table 2. Am29SL800DT Top Boot Block Sector Address Table
Address Range (in hexadecimal)
Sector Size
(Kbytes/
(x8)
(x16)
Sector
SA0
A18
0
A17
0
A16
0
A15
0
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Kwords)
Address Range
Address Range
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–F7FFFh
F8000h–F9FFFh
FA000h–FBFFFh
FC000h–FFFFFh
00000h–07FFFh
08000h–0FFFFh
10000h–17FFFh
18000h–1FFFFh
20000h–27FFFh
28000h–2FFFFh
30000h–37FFFh
38000h–3FFFFh
40000h–47FFFh
48000h–4FFFFh
50000h–57FFFh
58000h–5FFFFh
60000h–67FFFh
68000h–6FFFFh
70000h–77FFFh
78000h–7BFFFh
7C000h–7CFFFh
7D000h–7DFFFh
7E000h–7FFFFh
SA1
0
0
0
1
SA2
0
0
1
0
SA3
0
0
1
1
SA4
0
1
0
0
SA5
0
1
0
1
SA6
0
1
1
0
SA7
0
1
1
1
SA8
1
0
0
0
SA9
1
0
0
1
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
8/4
1
1
1
1
1
1
X
16/8
10
Am29SL800D
27546A6 January 23, 2007
AMD [ AMD ]
