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A800DB90PF 参数 Datasheet PDF下载

A800DB90PF图片预览
型号: A800DB90PF
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位( 1一M× 8位/ 512的K× 16位) CMOS 1.8伏只超低电压闪存 [8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory]
分类和应用: 闪存
文件页数/大小: 46 页 / 1066 K
品牌: AMD [ AMD ]
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D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29SL800D is an 8 Mbit, 1.8 V volt-only Flash-  
memory organized as 1,048,576 bytes or 524,288  
words. The device is offered in 48-pin TSOP and 48-  
ball FBGA packages. The word-wide data (x16)  
appears on DQ15–DQ0; the byte-wide (x8) data  
appears on DQ7–DQ0. This device is designed to be  
programmed and erased in-system with a single 1.8  
During erase, the device automatically times the erase  
pulse widths and verifies proper cell margin.  
The host system can detect whether a program or  
erase operation is complete by observing the RY/BY#  
pin, or by reading the DQ7 (Data# Polling) and DQ6  
(toggle) status bits. After a program or erase cycle has  
been completed, the device is ready to read array data  
or accept another command.  
volt V supply. No V is for write or erase operations.  
CC  
PP  
The device can also be programmed in standard  
EPROM programmers.  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is fully  
erased when shipped from the factory.  
The standard device offers access times of 90, 100,  
120, and 150 ns, allowing high speed microprocessors  
to operate without wait states. To eliminate bus conten-  
tion, the device has separate chip enable (CE#), write  
enable (WE#) and output enable (OE#) controls.  
Hardware data protection measures include a low  
V
detector that automatically inhibits write opera-  
CC  
tions during power transitions. The hardware sector  
protection feature disables both program and erase  
operations in any combination of the sectors of  
memory. This can be achieved in-system or via pro-  
gramming equipment.  
The device requires only a single 1.8 volt power  
supply for both read and write functions. Internally  
generated and regulated voltages are provided for the  
program and erase operations.  
The device is entirely command set compatible with the  
JEDEC single-power-supply Flash standard. Com-  
mands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state-machine that  
controls the erase and programming circuitry. Write  
cycles also internally latch addresses and data needed  
for the programming and erase operations. Reading  
data out of the device is similar to reading from other  
Flash or EPROM devices.  
The Erase Suspend feature enables the user to put  
erase on hold for any period of time to read data from,  
or program data to, any sector that is not selected for  
erasure. True background erase can thus be achieved.  
The hardware RESET# pin terminates any operation  
in progress and resets the internal state machine to  
reading array data. The RESET# pin may be tied to the  
system reset circuitry. A system reset would thus also  
reset the device, enabling the system microprocessor  
to read the boot-up firmware from the Flash memory.  
Device programming occurs by executing the program  
command sequence. This initiates the Embedded  
Program algorithm—an internal algorithm that auto-  
matically times the program pulse widths and verifies  
proper cell margin. The Unlock Bypass mode facili-  
tates faster programming times by requiring only two  
write cycles to program data instead of four.  
The device offers two power-saving features. When  
addresses have been stable for a specified amount of  
time, the device enters the automatic sleep mode.  
The system can also place the device into the standby  
mode. Power consumption is greatly reduced in both  
these modes.  
Device erasure occurs by executing the erase  
command sequence. This initiates the Embedded  
Erase algorithm—an internal algorithm that automati-  
cally preprograms the array (if it is not already  
programmed) before executing the erase operation.  
AMD’s Flash technology combines years of Flash  
memory manufacturing experience to produce the  
highest levels of quality, reliability and cost effective-  
ness. The device electrically erases all bits within a  
sector simultaneously via Fowler-Nordheim tunneling.  
The data is programmed using hot electron injection.  
2
Am29SL800D  
27546A6 January 23, 2007  
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