D A T A S H E E T
AC CHARACTERISTICS
Table 11. Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms) to Read or Write
tREADY
Max
20
µs
(see Note)
RESET# Pin Low (NOT During Embedded Algorithms) to Read or
Write (see Note)
tREADY
Max
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
RESET# High Time Before Read (see Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Min
Min
Min
Min
500
200
20
ns
ns
µs
ns
0
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY#
t
RB
CE#, OE#
RESET#
t
RP
Figure 14. RESET# Timings
January 23, 2007 27546A6
Am29SL800D
29
AMD [ AMD ]
