D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std
Description
Test Setup
-100
-120
-150
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Address to Output Delay
Min
100
100
120
150
150
ns
CE# = VIL
OE# = VIL
tAVQV
tACC
Max
120
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL
Max
Max
Max
Max
Min
100
35
120
50
16
16
0
150
65
ns
ns
ns
ns
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
30
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11, on page 34 and Table 14, on page 34 for
test specifications.
.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
January 23, 2007 21635C5
Am29SL160C
35
AMD [ AMD ]
