D A T A S H E E T
Command Definitions
Table 12. Am29SL160C Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Data Addr Data
Fifth
Sixth
Addr Data Addr Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
RD
F0
Word
Manufacturer ID
Byte
2AA
555
555
4
AA
55
55
90
90
X00
X01
01
AAA
22E4/
22E7
Device ID
Word
555
2AA
555
(Top Boot/Bottom
4
AA
Boot)
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
AAA
555
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
PA
AAA
555
X02
X03
E4/E7
SecSi Sector Factory
Protect
4
4
3
4
4
3
AA
AA
AA
AA
AA
AA
55
55
55
55
55
55
90
90
88
90
A0
20
AAA
555
AAA
555
X06
(SA)X02
(SA)X04
Sector Protect Verify
(Note 9)
AAA
555
AAA
555
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
AAA
555
AAA
555
XXX
PA
00
AAA
555
AAA
555
PD
AAA
555
AAA
555
Unlock Bypass
AAA
XXX
AAA
Unlock Bypass Program (Note 10)
Unlock Bypass Reset (Note 11)
A0
90
PD
00
2
2
BA
555
AAA
555
AAA
BA
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Word
Sector Erase
Byte
6
SA
AAA
AAA
Erase Suspend (Note 12)
Erase Resume (Note 13)
1
1
B0
30
BA
Word
CFI Query (Note 14)
Byte
55
1
98
AA
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1, on page 9 for description of bus operations.
9. The data is 00h for an unprotected sector and 01h for a protected
sector. Data bits DQ1ꢀ–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
4. Data bits DQ1ꢀ–DQ8 are don’t cares in byte mode.
11. The Unlock Bypass Reset command is required to return to the
read mode when in the unlock bypass mode.
ꢀ. Unless otherwise noted, address bits A19–A11 are don’t cares.
6. No unlock or command cycles required when in read mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when in the autoselect mode, or if DQꢀ goes high (while providing
status information).
13. The Erase Resume command is valid only during the Erase
Suspend mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle.
14. Command is valid when device is ready to read array data or
when device is in autoselect mode.
26
Am29SL160C
21635C5 January 23, 2007
AMD [ AMD ]
