D A T A S H E E T
data. Standard microprocessor read cycles that assert
If the system asserts VHH on the pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode and uses the higher voltage on the pin to reduce
the time required for program operations. The system
would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH
from the WP#/ACC pin returns the device to normal
operation.
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” on page 21 for more infor-
mation. Refer to the AC table for timing specifications
and to Figure 13, on page 35 for the timing diagram.
ICC1 in the DC Characteristics table represents the
active current specification for reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” on page 27 for more information, and to “AC
Characteristics” on page 35 for timing diagrams.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
Standby Mode
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” on page 9
for more information.
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
“Word/Byte Program Command Sequence” on
page 22 contains details on programming data to the
device using both standard and Unlock Bypass
command sequences.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.2 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.2 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (tCE) for read access when the device
is in either of these standby modes, before it is ready to
read data.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2, on page 12 and
Table 3, on page 13 indicate the address space that
each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector.
The “Command Definitions” on page 21 contains
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to “RESET#: Hard-
ware Reset Pin” on page 10.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to “Autoselect Mode” on page 14
and “Autoselect Command Sequence” on page 22 for
more information.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 50
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The “AC
Characteristics” on page 35 contains timing specifica-
tion tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operation
through the ACC function, which is one of two functions
provided by the WP#/ACC pin. This function is primarily
intended to allow faster in-system programming of the
device during the system production process.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
10
Am29SL160C
21635C5 January 23, 2007
AMD [ AMD ]
