D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. Table 1 lists the device bus
operations, the inputs and control levels they require,
and the resulting output. The following subsections
describe each of these operations in further detail.
Table 1. Am29SL160C Device Bus Operations
DQ8–DQ15
DQ0– BYTE# BYTE#
Addresses
(Note 1)
Operation
CE# OE# WE# RESET# WP#/ACC
DQ7
= VIH
= VIL
Read
Write
(Program/Erase)
L
L
H
H
X
AIN
DOUT
DOUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
L
H
L
H
(Note 3)
AIN
DIN
DIN
VCC
0.2 V
VCC
0.2 V
Standby
X
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Protect
(Note 2)
L
H
L
VID
X
DIN
X
X
Sector Address,
(Note 3) A6 = H, A1 = H,
A0 = L
Sector Unprotect
(Note 2)
L
H
X
L
VID
VID
DIN
DIN
X
X
Temporary Sector
Unprotect
X
X
(Note 3)
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 1.0 V, VHH = 10 0.ꢀ V, X = Don’t Care, AIN = Address In, DIN = Data In,
DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector
Block Protection and Unprotection” on page 1ꢀ.
3. If WP#/ACC = VIL, the two outermost boot sectors are protected. If WP#/ACC = VIH, the two outermost boot sectors are
protected or unprotected as previously set by the system. If WP#/ACC = VHH, all sectors, including the two outermost boot
sectors, are unprotected.
Word/Byte Configuration
Requirements for Reading Array Data
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
January 23, 2007 21635C5
Am29SL160C
9
AMD [ AMD ]
