AMD
Message Transfer Control Logic
Message Transfer Control Logic
Data
Source
Data
Source
Command
Source
Command
Source
8
9
3
4
DI0 – DI7
CI0 – CI3
DI0 – DI8
CI0 – CI2
STRB
ACK
STRB ACK
SEROUT+
SEROUT+
SEROUT–
TAXI TX #2
TAXI TX #1
SEROUT–
(Note 1)
(Note 1)
X2
X1
TLS
DMS
CLK
X2
X1
TLS
DMS
CLK
*
(Note 2)
3.3 MHz to
17.5 MHz
To Other Stages
(Note 4)
(Note 4)
3.3 MHz to
17.5 MHz
3.3 MHz to
17.5 MHz
*
*
X1
X2
DMS
CLOCK
X2
SERIN+ SERIN–
CNB
SERIN+ SERIN–
CNB
X1
DMS
CLOCK
TAXI RX #1
IGM
VLTN
TAXI RX #2
IGM
VLTN
DO0 – DO8
CO0
– CO2
DO0– DO7
CO0 – CO3 CSTRB
4
DSTRB
DSTRB
CSTRB
9
8
3
Data
Destination
Command
Destination
Data
Destination
Command
Destination
Data Path Control Logic
Data Path Control Logic
07370F-12
Notes:
1. DMS = GND = 8 Bit Mode
2. DMS = VCC = 9 Bit Mode
TLS = GND = Local Mode
TLS = GND = Local Mode
Pin 11 = Don’t Connect = Local Mode
Pin 11 = Don’t Connect = Local Mode
3. Two 8-bit local mode systems in parallel will result in an effective data rate of 200 Mbps.
4. Use inverter for operation above 140 MHz only.
*Alternatively, the X1 inputs may be driven by external TTL frequency sources.
Figure 3. TAXIchip System in Local Mode
Am7968/Am7969
19
AMD [ AMD ]
