AMD
Am7969 TAXIchip Receiver
DO0 – DO7
Parallel Data Out (TTL Outputs)
CLK
Clock (TTL Output)
These eight outputs reflect the most recent Data re-
ceived by the Am7969 Receiver.
This is a free-running clock output which runs at the byte
rate, and is synchronous with the serial input. It falls at
the time that the Decoder Latch is loaded from the
Shifter, and rises at mid-byte. The CLK output of the Re-
ceiver is not suitable as a frequency source for another
TAXI Transmitter or Receiver. It is intended to be used
by the host system as a clock synchronous with the re-
ceived data.
DO8/CO3
Parallel Data (8) Out or Command (3) Out
(TTL Output)
DO8/CO3 output will be either a Data or Command bit,
depending upon the state of DMS.
DO9/CO2
Parallel Data (9) Out or Command (2) Out
(TTL Output)
CNB
Catch Next Byte Input (TTL Input)
DO9/CO2 output will be either a Data or Command bit,
depending upon the state of DMS.
If this input is connected to the CLK output, the Receiver
will be in the Local mode, and each received byte will be
captured, decoded and latched to the outputs.
DSTRB
Output Data Strobe (TTL Output)
If the CNB input is HIGH, it allows the Am7969 Receiver
to capture the first byte after a sync. The Am7969 Re-
ceiver will wait for another sync before latching the data
out, and capturing another. If CNB is toggled LOW, it will
react as if it had decoded a sync byte.
The rising edge of this output signals the presence of
new Data on the DO0 – DO9 lines. Data is valid just be-
fore the rising edge of DSTRB.
GND1, GND2
Ground
In Cascade mode, CNB input is typically connected to
an upstream Am7969’s IGM output. The first Am7969
Receiver in line will have its CNB input connected to
GND1 is a TTL I/O Ground, GND2 is an internal Logic
and Analog Ground.
VCC
.
IGM
For Am7969-175 applications, an inverter is required
between CLK and CNB for speeds above 140 MHz. See
Figure 3 and Timing Specifications T47A, T47B, T48,
and T49.
I-Got-Mine (TTL Output)
This pin signals cascaded Am7969 Receivers that their
upstream neighbor has captured its assigned data byte.
IGM falls at the mid-byte when the first half of a sync
byte is detected in the Shifter. It rises at mid-byte when it
detects a non-sync pattern. During Local mode opera-
tion the IGM signal is undefined.
CO0 – CO1
Parallel Command Out (TTL Output)
These two outputs reflect the most recent Command
data received by the Am7969 Receiver.
RESET
PLL RESET (Input)
CSTRB
Command Data Strobe (TTL Output)
This pin is normally left open, but can be momentarily
grounded to force the internal PLL to reactivate lock.
This allows for correction in the unlikely occurance of
PLL Lockup on application of power.
The rising edge of this output signals the presence of
new Command data on the CO0 – CO3 lines. Command
bits are valid just before the rising edge of CSTRB.
RESET has an internal pull-up resistor (50 K nominal)
which causes it to float high when left unconnected.
DMS
Data Mode Select (Input)
DMS selects the Data pattern width. When it is wired to
GND, the Am7969 Receiver will assume Data to be
eight bits wide, with four bits of Command. When it is
wired to VCC the Am7969 Receiver will assume Data to
be nine bits wide, with three bits of Command. If DMS is
left floating (or terminated to 1/2 VCC), the Am7969 Re-
ceiver will assume Data to be ten bits wide, with two bits
of Command.
If this board is driven by a board Reset signal, an open
drain (or open collector) style output should be used to
insure the High level signal is at VCC.
SERIN+, SERIN–
Differential Serial Data In (ECL Inputs)
Data is shifted serially into the Shifter. The SERIN+ and
SERIN– differential ECL inputs accept ECL voltage
8
Am7968/Am7969
AMD [ AMD ]
