AMD
TAXI Technical Information Publication #89-08
S u b je c t : TAXI Re c e ive r Lo c k Tim e
Qu e s t io n :
In a fully operational system in which both the Transmitter and Receiver are powered
on, how long will it take for the Receiver to lock to new data after a quiet line?
An s w e r:
When data transmission stops and the link becomes quiet, the TAXI Receiver PLL will
drift to its natural resting frequency which by design, is less than 3% away from the
reference frequency applied at the X1 pin.
When data appears on the line, the Receiver PLL will achieve phase lock in a time
which is proportional to the incoming data edge density and PLL loop bandwidth.
Because this lock time is dependent on the data being transmitted, the time it takes for
the receiver to lock will depend on the specific system application. In Section 3.3, three
types of data are represented and their calculated lock times are shown. By dividing the
lock time for a specific data pattern by the X1 clock period, the number of bytes to lock
the PLL can be calculated.
Because time to lock is dependent on many variables, it is represented as a typical time.
If time to lock is critical to the specific application, we suggest you allow at least the
times shown.
Although there is no guaranteed specification for time to lock, a test is run (using a JK
pattern) as part of AMD outgoing tests to ensure that all devices can achieve lock within
a reasonable time. The test is performed by sending JKs for 640 µs, and then without
interruption, a full rate functional test is run. For the test to pass, the PLL must lock to
the JK pattern and then track the incoming data perfectly.
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TAXIchip Integrated Circuits Technical Manual
AMD [ AMD ]
