Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
Synchronous RD# FIFO Timing
Functional Operation Range (VCC=5.0V 5%, 0 C to 70 C T 50 pf load on outputs).
Symbol
Parameter
SELECT# Setup to BPCLK Rising Edge
SELECT# Hold from BPCLK Rising Edge
ADR[6:2] Setup to BPCLK Rising Edge
ADR[6:2] Hold from BPCLK Rising Edge
BE[3:0]# Setup to BPCLK Rising Edge
BE[3:0]# Hold from BPCLK Rising Edge
RD# Low to DQ[31:0] Driven
Min
10
2
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
30
4
112
112a
116
14
1
34
29
4
4
1
116a
120
120a
125
128
156
157
124
124a
127
9
3
17
8
RD# High to DQ[31:0] Float
RDEMPTY Status Valid to BPCLK Rising Edge
FRF Status Valid to BPCLK Rising Edge
RD# Setup to BPCLK Rising Edge
13
74
31
11
1
4
RD# Hold from BPCLK Rising Edge
DQ[31:0] Valid from BPCLK Rising Edge
6
Notes:
1. Data is valid for 22ns for a 31ns t
RD# Setup.
124
2. RD# and SELECT# must both be asserted to dric=ve DQ[31:0] - delay is from the last one asserted.
3. When increasing Setup times, ADR[6:2], BE[3:0]#, SELECT#, and RD# timing relations remain relative to each other as shown.
4. Min and Max are indicated to allow increased valid data time as shown by dashed lines. First accesses are async.
Figure 100. Synchronous RD# FIFO Timing
BPCLK
t112 Max
t112
t112a
SELECT#
t116
t116a
ADR[6:2]
t120
t120a
BE[3:0]#
t125
DQ[31:0]
t128
t124
t124a
RD#
t156
5ns
RDEMPTY
t157
FRF
AMCC Confidential and Proprietary
DS1527
183
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
