Revision 1.02 – June 27, 2006
S5935 – PCI Product
Data Book
To write data into the APTD Register, the PTBEn# out-
put and the BEn# input must both be asserted. The
following describes how APTD Register writes are
controlled:
This process continues until all bytes have been read
from the APTD Register. During clock 5, RD# is deas-
serted and PTRDY# is asserted. PTRDY# is sampled
by the S5935 at the rising edge of clock 6, and the cur-
rent data phase is completed. PTATN# is deasserted
and new data can be written from the PCI bus. In this
example, the byte enables are asserted, sequentially,
from BE0# to BE3#. This is not required, bytes may be
accessed in any order.
Write BYTE3 if PTBE3# AND BE3# are asserted
Write BYTE2 if PTBE2# AND BE2# are asserted
Write BYTE1 if PTBE1# AND BE1# are asserted
Write BYTE0 if PTBE0# AND BE0# are asserted
New data is written by the PCI initiator and is available
in the APTD Register during clock 7. RD# is asserted
and the byte enables are cycled again. With each new
data from the PCI bus, the Add-On sequences through
the byte enables to access APTD via DQ[7:0].
After each byte is written into the Pass-Thru data reg-
ister, its corresponding PTBE[3:0]# output is
deasserted. This allows Add-On logic to monitor which
bytes have been written, and which bytes remain to be
written. When all bytes requested by the PCI initiator
have been written, the PTBE[3:0]# are all be deas-
serted, and the Add-On asserts PTRDY#.
For 16-bit peripheral devices, the byte steering works
in the same way. Because the Add-On data bus is 16-
bits wide, only two 16-bit cycles are required to access
the entire APTD Register. Two byte enables can be
asserted during each access.
Figure 11 shows Pass-Thru operation for a region
defined for an 8-bit Add-On bus interface. As the 8-bit
device is connected only to DQ[7:0], the device must
access APTD one byte at a time.
In Figure 11, RD# is held low and the byte enables are
changed each clock. This assumes the Add-On can
accept data at one byte per clock. This is the fastest
transfer possible. For slower devices, wait states may
be added.
The PCI initiator has performed a 32-bit write of
08D49A30h to Pass-Thru region zero. PTBE[3:0]# are
all asserted. At clock 1, the Add-On begins reading the
APTD Register (asserting SELECT#, ADR[6:2], and
RD#). Add-On logic asserts BE0#, and BYTE0 of
APTD is driven on DQ[7:0]. At the rising edge of clock
2, BE0# is sampled by the S5935 and PTBE0# is
deasserted. PTBE[3:1]# are still asserted.
As long as the byte enables remain in a given state,
the corresponding byte of the APTD Register is con-
nected to the DQ bus (the RD# or WR# pulse may
also be lengthened). Each access may be extended
for slower Add-On devices, but extending individual
data phases for Pass-Thru cycles may result in the
S5935 requesting retries by the initiator.
During clock 2, only BE1# is activated, and BYTE1 of
APTD is driven on DQ[7:0]. At the rising edge of clock
3, BE1# is sampled by the S5935 and PTBE1# is
deasserted. PTBE[3:2]# are still asserted.
Figure 90. Pass-Thru Write to an 8-bit Add-On Device
1
2
3
4
5
6
7
8
9
10
11
12
13
BPCLK
PTATN#
PTWR
Fh
0h
0
1h
3h
Bh
7h
7h
Fh
Fh
0h
1h
3h
Bh
7h
7h
Fh
PTBE[3:0]#
PTNUM[1:0]
PTBURST#
SELECT#
BE[3:0]#
ADR[6:2]
RD#
Fh
Eh
Dh
Eh
Dh
Fh
3Ch
2Ch
3Ch
ADDR
30h
9Ah
D4h
08h
DDh
CCh
BBh
AAh
DQ[7:0]
PTADR#
PTRDY#
Note: 8 Bit Mode BE’s are E, D, B, 7; 16 Bit Mode BE’s are C, 3.
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DS1527
169
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
