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S5935_07 参数 Datasheet PDF下载

S5935_07图片预览
型号: S5935_07
PDF下载: 下载PDF文件 查看货源
内容描述: PCI产品 [PCI Product]
分类和应用: PC
文件页数/大小: 204 页 / 3916 K
品牌: AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
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Revision 1.02 – June 27, 2006  
S5935 – PCI Product  
Data Book  
Add-On FIFO Status Indicators  
Signal  
RDFIFO#  
WRFIFO#  
FRC#  
Function  
The Add-On interface implements FIFO status pins to  
indicate the full and empty conditions of the PCI to  
Add-On and Add-On to PCI FIFOs. These may be  
used by the Add-On to allow data transfers between  
the FIFO and memory, a peripheral, or even a cas-  
caded external FIFO. The RDEMPTY and WRFULL  
status outputs are always available to the Add-On.  
Additional status signals are multiplexed with the byte-  
wide, non-volatile memory interface pins. If the S5935  
is configured for Add-On initiated bus mastering, these  
status signals also become available to the Add-On.  
FIFO status is also indicated by bits in the Add-On  
General Control/Status and Bus Master Control/Status  
Registers. The table below lists all FIFO status outputs  
and their functions.  
Reads data from the PCI to Add-On FIFO  
Writes data into the Add-On to PCI FIFO  
Reset PCI to Add-On FIFO pointers and  
1
status indicators  
FWC#  
AMREN  
AMWEN  
Reset Add-On to PCI FIFO pointers and  
1
status indicators  
Enable bus mastering for Add-On initiated  
1
PCI reads  
Enable bus mastering for Add-On initiated  
1
PCI writes  
1. These signals are only available when a serial non-volatile mem-  
ory is used and the S5935 is configured for Add-On initiated bus  
mastering.  
Signal  
Function  
PCI Bus Mastering with the FIFO  
RDEMPTY  
Indicates empty condition of the PCI to  
Add-On FIFO  
The S5935 may initiate PCI bus cycles through the  
FIFO interface. The S5935 allows blocks of data to be  
transferred to and from the Add-On by specifying a  
source/destination address on the PCI bus and a  
transfer byte count. This DMA capability allows data to  
be transferred across the PCI bus without host CPU  
intervention.  
WRFULL  
FRF  
Indicates full condition of the Add-On to  
PCI FIFO  
Indicates full condition of the PCI to Add-  
1
On FIFO  
FWE  
Indicates the empty condition of the Add-  
Initiating a bus master transfer requires programming  
the appropriate address registers and transfer byte  
counts. This can be done from either the PCI interface  
or the Add-On interface. Initiating bus master transfers  
from the add-on is advantageous because the host  
CPU does not have to intervene for the S5935 to  
become a PCI Initiator. At the end of a transfer the  
S5935 may generate an interrupt to either the PCI bus  
(for PCI initiated transfers) or Add-On interface (for  
Add-On initiated transfers).  
1
On to PCI FIFO  
1. These signals are only available when a serial non-volatile mem-  
ory is used and the device is configured for Add-On initiated bus  
mastering.  
Add-On FIFO Control Signals  
The Add-On interface implements FIFO control pins to  
manipulate the S5935 FIFOs. These may be used by  
Add-On to control data transfer between the FIFO and  
memory, a peripheral, or even a cascaded external  
FIFO. The RDFIFO# and WRFIFO# inputs are always  
available. These pins allow direct access to the FIFO  
without generating a standard Add-On register access  
using RD#, WR#, SELECT#, address pins and the  
byte enables.  
Add-On Initiated Bus Mastering  
If bit 7 in location 45h of an external serial non-volatile  
memory is zero, the Master Read Address Register  
(MRAR), Master Write Address Register (MWAR),  
Master Read Transfer Count (MRTC), and Master  
Write Transfer Count (MWTC) are accessible only  
from the Add-On interface. Add-On initiated bus mas-  
tering is not possible when a byte-wide boot device is  
used due to shared device pins. When configured for  
Add-On initiated bus mastering, the S5935 transfers  
data until the transfer count reaches zero, or it may be  
configured to ignore the transfer count.  
Additional control signals are multiplexed with the  
byte-wide, non-volatile memory interface pins. If a  
serial non-volatile memory is used and the S5935 is  
configured for Add-On initiated bus mastering, these  
control signals also become available. For PCI initi-  
ated bus mastering, AMREN, AMWEN, FRC#, and  
FWC# functionality is always available through bits in  
the Bus Master Control/Status and Add-On General  
Control/Status Registers. The FIFO control inputs are  
listed below.  
AMCC Confidential and Proprietary  
DS1527  
137